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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2018-10-31 12:27:46 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2018-10-31 12:27:46 +0100 |
| commit | 635aeaa20ffdf6e794f180cc8e053e8dc46db760 (patch) | |
| tree | ca53d051f9bcfe311d00dfe37c8bae70900042e0 /gcc/tree-outof-ssa.c | |
| parent | aac1c11ce4edd9c2e6af7e9ee8abcaba98d8741f (diff) | |
| download | gcc-635aeaa20ffdf6e794f180cc8e053e8dc46db760.zip gcc-635aeaa20ffdf6e794f180cc8e053e8dc46db760.tar.gz gcc-635aeaa20ffdf6e794f180cc8e053e8dc46db760.tar.bz2 | |
[ARC] Handle store cacheline hazard.
Handle store cacheline hazard for A700 cpus by inserting two NOP_S
between ST ST LD or their logical equivalent (like ST ST NOP_S NOP_S
J_L.D LD)
gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-arch.h (ARC_TUNE_ARC7XX): New tune value.
* config/arc/arc.c (arc_active_insn): New function.
(check_store_cacheline_hazard): Likewise.
(workaround_arc_anomaly): Use check_store_cacheline_hazard.
(arc_override_options): Disable delay slot scheduler for older
A7.
(arc_store_addr_hazard_p): New implementation, old one renamed to
...
(arc_store_addr_hazard_internal_p): Renamed.
(arc_reorg): Don't combine into brcc instructions which are part
of hardware hazard solution.
* config/arc/arc.md (attr tune): Consider new arc7xx tune value.
(tune_arc700): Likewise.
* config/arc/arc.opt (arc7xx): New tune value.
* config/arc/arc700.md: Improve A7 scheduler.
From-SVN: r265676
Diffstat (limited to 'gcc/tree-outof-ssa.c')
0 files changed, 0 insertions, 0 deletions