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| author | Michael Meissner <meissner@linux.ibm.com> | 2020-08-07 01:03:22 -0400 |
|---|---|---|
| committer | Michael Meissner <meissner@linux.ibm.com> | 2020-08-07 01:03:22 -0400 |
| commit | eb5f081c16bde273f0b3c24b5929c822ae502a4f (patch) | |
| tree | d879c763ff5895ab80d06414ae575854f50bb057 /gcc/tree-if-conv.c | |
| parent | f8ac30f1653ff69706c35af6d725f1d330600f11 (diff) | |
| download | gcc-eb5f081c16bde273f0b3c24b5929c822ae502a4f.zip gcc-eb5f081c16bde273f0b3c24b5929c822ae502a4f.tar.gz gcc-eb5f081c16bde273f0b3c24b5929c822ae502a4f.tar.bz2 | |
Power10: Add BRD, BRW, and BRH support.
This patch adds support for the ISA 3.1 (power10) instructions that does a byte
swap of values in GPR registers.
gcc/
2020-08-07 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (bswaphi2_reg): Add ISA 3.1 support.
(bswapsi2_reg): Add ISA 3.1 support.
(bswapdi2): Rename bswapdi2_xxbrd to bswapdi2_brd.
(bswapdi2_brd,bswapdi2_xxbrd): Rename. Add ISA 3.1 support.
gcc/testsuite/
2020-08-07 Michael Meissner <meissner@linux.ibm.com>
* gcc.target/powerpc/bswap-brd.c: New test.
* gcc.target/powerpc/bswap-brw.c: New test.
* gcc.target/powerpc/bswap-brh.c: New test.
Diffstat (limited to 'gcc/tree-if-conv.c')
0 files changed, 0 insertions, 0 deletions