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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-11-21 20:35:21 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-11-21 20:35:21 +0000 |
| commit | d85e598a59f826d0fbd4af684c680b68970e6cda (patch) | |
| tree | 66b37a5fdb0f33b31a0b7685fee5fb8fbc0a964d /gcc/tree-if-conv.c | |
| parent | 699e8cb7b4d067cabff5a92bdbbb2d0d0dddc262 (diff) | |
| download | gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.zip gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.tar.gz gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.tar.bz2 | |
rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in...
[gcc]
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movdi_internal32): Change constraints
so that DImode can be allocated to FP/vector registers in more
cases, and we can avoid direct move operations. If the register
needs reloading, prefer GPRs over FP/vector registers. In the
case of FPR vs. Altivec registers, prefer FPR registers unless we
have the ISA 3.0 reg+offset scalar instructions.
(movdi_internal64): Likewise.
[gcc/testsuite]
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
to be generated instead of FCTIWUZ or FCTIWZ.
From-SVN: r242679
Diffstat (limited to 'gcc/tree-if-conv.c')
0 files changed, 0 insertions, 0 deletions