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| author | Xionghu Luo <luoxhu@linux.ibm.com> | 2021-10-19 04:02:04 -0500 |
|---|---|---|
| committer | Xionghu Luo <luoxhu@linux.ibm.com> | 2021-10-19 04:02:04 -0500 |
| commit | 0910c516a3d72af048af27308349167f25c406c2 (patch) | |
| tree | 740baf03c4bc90f1fb37c01dd77f495f5003caaf /gcc/tree-if-conv.c | |
| parent | d2161caffbb56a434776608af4e4491b59e508c8 (diff) | |
| download | gcc-0910c516a3d72af048af27308349167f25c406c2.zip gcc-0910c516a3d72af048af27308349167f25c406c2.tar.gz gcc-0910c516a3d72af048af27308349167f25c406c2.tar.bz2 | |
rs6000: Remove unspecs for vec_mrghl[bhw]
vmrghb only accepts permute index {0, 16, 1, 17, 2, 18, 3, 19, 4, 20,
5, 21, 6, 22, 7, 23} no matter for BE or LE in ISA, similarly for vmrglb.
Remove UNSPEC_VMRGH_DIRECT/UNSPEC_VMRGL_DIRECT pattern as vec_select
+ vec_concat as normal RTL.
Tested pass on P8LE, P9LE and P8BE{m32}.
gcc/ChangeLog:
2021-10-19 Xionghu Luo <luoxhu@linux.ibm.com>
* config/rs6000/altivec.md (*altivec_vmrghb_internal): Delete.
(altivec_vmrghb_direct): New.
(*altivec_vmrghh_internal): Delete.
(altivec_vmrghh_direct): New.
(*altivec_vmrghw_internal): Delete.
(altivec_vmrghw_direct_<mode>): New.
(altivec_vmrghw_direct): Delete.
(*altivec_vmrglb_internal): Delete.
(altivec_vmrglb_direct): New.
(*altivec_vmrglh_internal): Delete.
(altivec_vmrglh_direct): New.
(*altivec_vmrglw_internal): Delete.
(altivec_vmrglw_direct_<mode>): New.
(altivec_vmrglw_direct): Delete.
* config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Adjust.
* config/rs6000/rs6000.c (altivec_expand_vec_perm_const):
Adjust.
* config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust.
(vsx_xxmrglw_<mode>): Adjust.
gcc/testsuite/ChangeLog:
2021-10-19 Xionghu Luo <luoxhu@linux.ibm.com>
* gcc.target/powerpc/builtins-1.c: Update instruction counts.
Diffstat (limited to 'gcc/tree-if-conv.c')
0 files changed, 0 insertions, 0 deletions