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authorChristophe Lyon <christophe.lyon@linaro.org>2020-09-25 10:40:18 +0000
committerChristophe Lyon <christophe.lyon@linaro.org>2020-09-25 10:41:14 +0000
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tree17f8721c045b0d803e2e5b2d903b9a82a13585fd /gcc/tree-if-conv.c
parent499b63048acd5e9ffd3c04061b531f6bf851dc00 (diff)
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testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c
Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the vtrn_half, vuzp_half and vzip_half started failing with vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no linkage vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no linkage vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no linkage This is because r11-3402 now always declares float64x2 variables for aarch64, leading to a duplicate declaration in these testcases. The fix is simply to remove these now useless declarations. These tests are skipped on arm*, so there is no impact on that target. 2020-09-25 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ PR target/71233 * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove declarations of vector, vector2, vector_res for float64x2 type. * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.
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