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author | Michael Collison <michael.collison@arm.com> | 2017-10-27 06:05:58 +0000 |
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committer | Michael Collison <collison@gcc.gnu.org> | 2017-10-27 06:05:58 +0000 |
commit | 22be0d084c010c8c798f397d628759d259b15a92 (patch) | |
tree | 8064bf46ae9e6631cad0fde860c06b6f09e943f9 /gcc/tree-eh.c | |
parent | acec245b359e4bb75f3ee635b2d367c84554860e (diff) | |
download | gcc-22be0d084c010c8c798f397d628759d259b15a92.zip gcc-22be0d084c010c8c798f397d628759d259b15a92.tar.gz gcc-22be0d084c010c8c798f397d628759d259b15a92.tar.bz2 |
aarch64.md (<optab>_trunc><vf><GPI:mode>2): New pattern.
2017-10-26 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64.md(<optab>_trunc><vf><GPI:mode>2):
New pattern.
(<optab>_trunchf<GPI:mode>2: New pattern.
(<optab>_trunc<vgp><GPI:mode>2: New pattern.
* config/aarch64/iterators.md (wv): New mode attribute.
(vf, VF): New mode attributes.
(vgp, VGP): New mode attributes.
(s): Update attribute with SImode and DImode prefixes.
* testsuite/gcc.target/aarch64/fix_trunc1.c: New testcase.
* testsuite/gcc.target/aarch64/vect-vcvt.c: Fix scan-assembler
directives to allow float or integer destination registers for
fcvtz[su].
From-SVN: r254133
Diffstat (limited to 'gcc/tree-eh.c')
0 files changed, 0 insertions, 0 deletions