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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-12 10:30:02 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-12 12:42:28 +0800 |
| commit | 9890f377013cf1e4f5b9fab8a7287a5380dade1f (patch) | |
| tree | e077a1bf194a55b42215dc2fcbf43680fa3aa0f1 /gcc/tree-cfg.cc | |
| parent | 8be20733b38c200f375cacf698d6b85e76055bcd (diff) | |
| download | gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.zip gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.tar.gz gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.tar.bz2 | |
RISC-V: Add TAREGT_VECTOR check into VLS modes
This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994
This is caused VLS modes incorrect codes int register allocation.
The original case trigger the ICE is fortran code but I can reproduce
with a C code.
gcc/ChangeLog:
PR target/110994
* config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.
gcc/testsuite/ChangeLog:
PR target/110994
* gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test.
Diffstat (limited to 'gcc/tree-cfg.cc')
0 files changed, 0 insertions, 0 deletions