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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2023-08-03 16:09:46 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2023-08-03 16:14:02 -0400 |
| commit | 9e3fd332959930efd3cabf222afbac910507d2f3 (patch) | |
| tree | 5841e3a314c2b782c654499ae87338ffc5c8d2c8 /gcc/tree-cfg.cc | |
| parent | c2a447d840476dbd99720f72809304a74abcf040 (diff) | |
| download | gcc-9e3fd332959930efd3cabf222afbac910507d2f3.zip gcc-9e3fd332959930efd3cabf222afbac910507d2f3.tar.gz gcc-9e3fd332959930efd3cabf222afbac910507d2f3.tar.bz2 | |
[PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
[ This is a partial commit. So not all the cases mentioned by
Xiao are currently handled. ]
This patch recognizes Zicond patterns when the select pattern
with condition eq or neq to 0 (using eq as an example), namely:
1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
various Zicond patterns.
* config/riscv/riscv.md (mov<mode>cc): Allow TARGET_ZICOND. Use
sfb_alu_operand for both arms of the conditional move.
Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
Diffstat (limited to 'gcc/tree-cfg.cc')
0 files changed, 0 insertions, 0 deletions