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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-05-09 21:25:23 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-05-09 21:25:23 +0000 |
| commit | bf2a705c2913fde78457d776b8fef8923836c1c4 (patch) | |
| tree | dcf9f016d42dcaf7d0dd0f114db64376ab68f8e8 /gcc/tree-cfg.c | |
| parent | 5285d5d3574ac90b8c14ac05ad205d2b4af30090 (diff) | |
| download | gcc-bf2a705c2913fde78457d776b8fef8923836c1c4.zip gcc-bf2a705c2913fde78457d776b8fef8923836c1c4.tar.gz gcc-bf2a705c2913fde78457d776b8fef8923836c1c4.tar.bz2 | |
re PR target/68163 (GCC on power8 does not issue the stxsspx instruction on power8)
[gcc]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
are now unused after splitting mov{sf,sd}_hardfloat.
(f32_lr2): Likewise.
(f32_lm): Likewise.
(f32_lm2): Likewise.
(f32_li): Likewise.
(f32_li2): Likewise.
(f32_lv): Likewise.
(f32_sr): Likewise.
(f32_sr2): Likewise.
(f32_sm): Likewise.
(f32_sm2): Likewise.
(f32_si): Likewise.
(f32_si2): Likewise.
(f32_sv): Likewise.
(f32_dm): Likewise.
(f32_vsx): Likewise.
(f32_av): Likewise.
(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
For movsf, order stores so the VSX stores occur before the GPR
store which encourages the register allocator to use a traditional
FPR instead of a GPR. For movsd, order the stores so that the GPR
store comes before the VSX stores to allow the power6 to work.
This is due to the power6 not having a 32-bit integer store
instruction from a FPR.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
[gcc/testsuite]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* gcc.target/powerpc/pr68163.c: New test.
From-SVN: r247819
Diffstat (limited to 'gcc/tree-cfg.c')
0 files changed, 0 insertions, 0 deletions