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| author | Jim Wilson <jimw@sifive.com> | 2020-11-13 18:12:24 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2020-11-13 18:12:35 -0800 |
| commit | dcf0dde488b81894124a6bb181c98e215d4dfdeb (patch) | |
| tree | 6dc1128f7efd75fa2b70bbf67e492a5573793ab9 /gcc/toplev.c | |
| parent | a4dd85e01599890286d9af5b106a1ab20e51169e (diff) | |
| download | gcc-dcf0dde488b81894124a6bb181c98e215d4dfdeb.zip gcc-dcf0dde488b81894124a6bb181c98e215d4dfdeb.tar.gz gcc-dcf0dde488b81894124a6bb181c98e215d4dfdeb.tar.bz2 | |
Asan changes for RISC-V.
We have only riscv64 asan support, there is no riscv32 support as yet. So I
need to be able to conditionally enable asan support for the riscv target. I
implemented this by returning zero from the asan_shadow_offset function. This
requires a change to toplev.c and docs in target.def.
gcc/
* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
(TARGET_ASAN_SHADOW_OFFSET): New.
* doc/tm.texi: Regenerated.
* target.def (asan_shadow_offset); Mention that it can return zero.
* toplev.c (process_options): Check for and handle zero return from
targetm.asan_shadow_offset call.
Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
Diffstat (limited to 'gcc/toplev.c')
| -rw-r--r-- | gcc/toplev.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/toplev.c b/gcc/toplev.c index e32dc28..e0e0e04 100644 --- a/gcc/toplev.c +++ b/gcc/toplev.c @@ -1834,7 +1834,8 @@ process_options (void) } if ((flag_sanitize & SANITIZE_USER_ADDRESS) - && targetm.asan_shadow_offset == NULL) + && ((targetm.asan_shadow_offset == NULL) + || (targetm.asan_shadow_offset () == 0))) { warning_at (UNKNOWN_LOCATION, 0, "%<-fsanitize=address%> not supported for this target"); |