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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2018-07-24 15:37:52 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2018-07-24 15:37:52 +0000 |
| commit | 8da03df56724152e4f524160b68e63c615d4632a (patch) | |
| tree | 8ff7ea849f6e10ce80490101868f49424376ea74 /gcc/testsuite | |
| parent | ebac3c0236c626f80b005af53505de5b79cba99d (diff) | |
| download | gcc-8da03df56724152e4f524160b68e63c615d4632a.zip gcc-8da03df56724152e4f524160b68e63c615d4632a.tar.gz gcc-8da03df56724152e4f524160b68e63c615d4632a.tar.bz2 | |
[GCC][AARCH64] Canonicalize aarch64 widening simd plus insns
Committed on behalf of matthew.malcomson@arm.com
2018-07-24 Matthew Malcomson <matthew.malcomson@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Split into...
(aarch64_<ANY_EXTEND:su>subw<mode>): ... This...
(aarch64_<ANY_EXTEND:su>addw<mode>): ... And this.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): Split into...
(aarch64_<ANY_EXTEND:su>subw<mode>_internal): ... This...
(aarch64_<ANY_EXTEND:su>addw<mode>_internal): ... And this.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Split into...
(aarch64_<ANY_EXTEND:su>subw2<mode>_internal): ... This...
(aarch64_<ANY_EXTEND:su>addw2<mode>_internal): ... And this.
* gcc.target/aarch64/vect-su-add-sub.c: New.
From-SVN: r262949
Diffstat (limited to 'gcc/testsuite')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c | 49 |
2 files changed, 53 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ca4d0bc..10488ca 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-07-24 Matthew Malcomson <matthew.malcomson@arm.com> + + * gcc.target/aarch64/vect-su-add-sub.c: New. + 2018-07-24 Jakub Jelinek <jakub@redhat.com> PR middle-end/86627 diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c new file mode 100644 index 0000000..338da54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* Ensure we use the signed/unsigned extend vectorized add and sub + instructions. */ +#define N 1024 + +int a[N]; +long c[N]; +long d[N]; +unsigned int ua[N]; +unsigned long uc[N]; +unsigned long ud[N]; + +void +add () +{ + for (int i = 0; i < N; i++) + d[i] = a[i] + c[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]saddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]saddw\[ \t\]+" 1 } } */ + +void +subtract () +{ + for (int i = 0; i < N; i++) + d[i] = c[i] - a[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]ssubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]ssubw\[ \t\]+" 1 } } */ + +void +uadd () +{ + for (int i = 0; i < N; i++) + ud[i] = ua[i] + uc[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]uaddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]uaddw\[ \t\]+" 1 } } */ + +void +usubtract () +{ + for (int i = 0; i < N; i++) + ud[i] = uc[i] - ua[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]usubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]usubw\[ \t\]+" 1 } } */ |