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author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2010-11-09 21:44:19 +0000 |
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committer | Michael Meissner <meissner@gcc.gnu.org> | 2010-11-09 21:44:19 +0000 |
commit | 219225619219329ca995c78627a894224df58b3f (patch) | |
tree | 188dd25b42448ce9d4a19497d84bc0355c876a5b /gcc/testsuite | |
parent | 9b999dc5ea45237cc7accead90a33e9c4a6893f5 (diff) | |
download | gcc-219225619219329ca995c78627a894224df58b3f.zip gcc-219225619219329ca995c78627a894224df58b3f.tar.gz gcc-219225619219329ca995c78627a894224df58b3f.tar.bz2 |
Improve powerpc floating point rounding
From-SVN: r166510
Diffstat (limited to 'gcc/testsuite')
-rw-r--r-- | gcc/testsuite/ChangeLog | 11 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/ppc-round.c | 37 |
4 files changed, 50 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3e451d0..19f58b1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2010-11-09 Michael Meissner <meissner@linux.vnet.ibm.com> + + * gcc.target/powerpc/ppc-fpconv-11.c: Use -mcpu=power5+, not + power5 to enable generation of FRIZ. + + * gcc.target/powerpc/ppc-round.c: New file, test (double)(int) + optimization. + + * gcc.target/powerpc/ppc-fpconv-2.c: Update # times lfiwax is + expected. + 2010-11-09 Jakub Jelinek <jakub@redhat.com> PR target/43808 diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c index f6d28cd..2eebbb4 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-options "-O2 -mcpu=power5 -ffast-math" } */ +/* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */ /* { dg-final { scan-assembler-not "xsrdpiz" } } */ /* { dg-final { scan-assembler "friz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c index f90a35b..e0a83422 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O2 -mcpu=power6 -ffast-math" } */ -/* { dg-final { scan-assembler-times "lfiwax" 1 } } */ +/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ /* { dg-final { scan-assembler-not "lfiwzx" } } */ /* { dg-final { scan-assembler-times "fcfid " 10 } } */ /* { dg-final { scan-assembler-not "fcfids" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c new file mode 100644 index 0000000..20262aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-times "stfiwx" 4 } } */ +/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ +/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ +/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ +/* { dg-final { scan-assembler-times "xscvsxddp" 2 } } */ +/* { dg-final { scan-assembler-times "fcfids" 2 } } */ +/* { dg-final { scan-assembler-not "lwz" } } */ +/* { dg-final { scan-assembler-not "stw" } } */ + +/* Make sure we don't have loads/stores to the GPR unit. */ +double +round_double_int (double a) +{ + return (double)(int)a; +} + +float +round_float_int (float a) +{ + return (float)(int)a; +} + +double +round_double_uint (double a) +{ + return (double)(unsigned int)a; +} + +float +round_float_uint (float a) +{ + return (float)(unsigned int)a; +} |