re PR target/6753 (gcc 3.1 produces wrong code when optimizing for pentium4)

	PR target/6753
	* config/i386/i386.md (sse_movdfcc, sse_movdfcc_eq): Use Y instead
	of x in constraints for clarity.
	(sse_mov?fcc split): abort if op2 == op3.
	(sse_movsfcc_const0_1, sse_movsfcc_const0_2, sse_movsfcc_const0_3,
	sse_movsfcc_const0_4): Add earlyclobber.
	(sse_movdfcc_const0_1, sse_movdfcc_const0_2, sse_movdfcc_const0_3,
	sse_movdfcc_const0_4): Likewise.  Use DFmode, not SFmode.
	Use Y instead of x in constraints.

	* gcc.dg/20020523-1.c: New test.

From-SVN: r53784

2 files changed, 69 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2681b7f..87ab261 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2002-05-23  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc.dg/20020523-1.c: New test.
+
 2002-05-23  Neil Booth  <neil@daikokuya.demon.co.uk>
 
 	* objc.dg/const-str-2.m: Update now that we stop after
diff --git a/gcc/testsuite/gcc.dg/20020523-1.c b/gcc/testsuite/gcc.dg/20020523-1.c
new file mode 100644
index 0000000..5ae3da5
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/20020523-1.c
@@ -0,0 +1,65 @@
+/* PR target/6753
+   This testcase was miscompiled because sse_mov?fcc_const0*
+   patterns were missing earlyclobber.  */
+/* { dg-do run { target i386-*-* } } */
+/* { dg-options "-march=pentium3 -msse -ffast-math -O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+float one = 1.f;
+
+void bar (float f)
+{
+  if (__builtin_memcmp (&one, &f, sizeof (float)))
+    abort ();
+}
+
+float foo (void)
+{
+  return 1.f;
+}
+
+typedef struct
+{
+  float t;
+} T;
+
+void bail_if_no_sse (void)
+{
+  int fl1, fl2;
+
+  /* See if we can use cpuid.  */
+  __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
+	   "pushl %0; popfl; pushfl; popl %0; popfl"
+	   : "=&r" (fl1), "=&r" (fl2)
+	   : "i" (0x00200000));
+  if (((fl1 ^ fl2) & 0x00200000) == 0)
+    exit (0);
+
+  /* See if cpuid gives capabilities.  */
+  __asm__ ("cpuid" : "=a" (fl1) : "0" (0) : "ebx", "ecx", "edx", "cc");
+  if (fl1 == 0)
+    exit (0);
+
+  /* See if capabilities include SSE (25th bit; 26 for SSE2).  */
+  __asm__ ("cpuid" : "=a" (fl1), "=d" (fl2) : "0" (1) : "ebx", "ecx", "cc");
+  if ((fl2 & (1 << 25)) == 0)
+    exit (0);
+}
+
+int main (void)
+{
+  int i;
+  T x[1];
+
+  bail_if_no_sse ();
+  for (i = 0; i < 1; i++)
+    {
+      x[i].t = foo ();
+      x[i].t = 0.f > x[i].t ? 0.f : x[i].t;
+      bar (x[i].t);
+    }
+
+  exit (0);
+}