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| author | Roger Sayle <roger@eyesopen.com> | 2006-06-19 14:57:17 +0000 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2006-06-19 14:57:17 +0000 |
| commit | fa00f91b0d55bf51b88bda778f519b8fc9a55b12 (patch) | |
| tree | c8e8a3185728aab4a7f079fa123272dd2738ec55 /gcc/testsuite | |
| parent | 096dce1b1bf69529a83de92dc17018c82b7b22ec (diff) | |
| download | gcc-fa00f91b0d55bf51b88bda778f519b8fc9a55b12.zip gcc-fa00f91b0d55bf51b88bda778f519b8fc9a55b12.tar.gz gcc-fa00f91b0d55bf51b88bda778f519b8fc9a55b12.tar.bz2 | |
re PR target/27861 (ICE in expand_expr_real_1, at expr.c:6916)
PR target/27861
* expmed.c (expand_shift): On SHIFT_COUNT_TRUNCATED targets, we may
have stripped a SUBREG from the shift count, so we may need to
convert_to_mode back to the type's mode before calling make_tree.
Use new_amount instead of amount to avoid expanding a tree twice.
* gcc.dg/pr27861-1.c: New test case.
From-SVN: r114773
Diffstat (limited to 'gcc/testsuite')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr27861-1.c | 67 |
2 files changed, 72 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ba44e8f..888e45a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2006-06-19 Roger Sayle <roger@eyesopen.com> + + PR target/27861 + * gcc.dg/pr27861-1.c: New test case. + 2006-06-19 Richard Guenther <rguenther@suse.de> PR middle-end/28045 diff --git a/gcc/testsuite/gcc.dg/pr27861-1.c b/gcc/testsuite/gcc.dg/pr27861-1.c new file mode 100644 index 0000000..cf269dc --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr27861-1.c @@ -0,0 +1,67 @@ +/* PR target/27861 */ +/* The following code used to cause an ICE during RTL expansion, as + expand shift was stripping the SUBREG of a rotate shift count, and + later producing a VAR_DECL tree whose DECL_RTL's mode didn't match + the VAR_DECL's type's mode. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct sim_state *SIM_DESC; +typedef enum +{ + SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG +} +SIM_RC; +typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__))); +typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__))); +typedef unsigned32 unsigned_address; +typedef unsigned_address address_word; +static __inline__ unsigned64 + __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift) +{ + unsigned64 result; + result = (((val) >> (shift)) | ((val) << ((64) - (shift)))); + return result; +} +typedef struct _sim_cpu sim_cpu; +enum +{ + TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX, +}; +typedef struct _trace_data +{ + char trace_flags[32]; +} +TRACE_DATA; +typedef enum +{ + nr_watchpoint_types, +} +watchpoint_type; +typedef struct _sim_watchpoints +{ + TRACE_DATA trace_data; +} +sim_cpu_base; +struct _sim_cpu +{ + sim_cpu_base base; +}; +struct sim_state +{ + sim_cpu cpu[1]; +}; +typedef address_word instruction_address; +do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x, + unsigned64 y) +{ + unsigned64 result; + result = ROTR64 (x, y); + { + if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0 + && (((&(((&(sd)->cpu[0])))->base.trace_data))-> + trace_flags)[TRACE_ALU_IDX] != 0)) + trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result)); + } +} + |