[AArch64] arm_neon.h - add vpaddd_f64, vpaddd_s64, vpaddd_u64 intrinsics

gcc/

	* config/aarch64/arm_neon.h (vpadd_<suf><8,16,32,64>): Move to
	correct alphabetical position.
	(vpaddd_f64): Rewrite using builtins.
	(vpaddd_s64): Move to correct alphabetical position.
	(vpaddd_u64): New.

gcc/testsuite/

	* gcc.target/aarch64/scalar_intrinsics.c (test_vpaddd_f64): New.
	(test_vpaddd_s64): Likewise.
	(test_vpaddd_s64): Likewise.
	* gcc.target/aarch64/simd/vpaddd_f64: New.
	* gcc.target/aarch64/simd/vpaddd_s64: New.
	* gcc.target/aarch64/simd/vpaddd_u64: New.

From-SVN: r213382

5 files changed, 106 insertions, 1 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1932ab1..a0c768f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2014-07-31  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* gcc.target/aarch64/scalar_intrinsics.c (test_vpaddd_f64): New.
+	(test_vpaddd_s64): Likewise.
+	(test_vpaddd_s64): Likewise.
+	* gcc.target/aarch64/simd/vpaddd_f64: New.
+	* gcc.target/aarch64/simd/vpaddd_s64: New.
+	* gcc.target/aarch64/simd/vpaddd_u64: New.
+
 2014-07-31  Charles Baylis  <charles.baylis@linaro.org>
 
 	PR target/61948
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index 624348e..0e288f2 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -293,13 +293,28 @@ test_vtstd_u64 (uint64_t a, uint64_t b)
   return res;
 }
 
-/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+/* { dg-final { scan-assembler-times "\\tfaddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
 
+float64_t
+test_vpaddd_f64 (float64x2_t a)
+{
+  return vpaddd_f64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 2 } } */
+
+int64_t
 test_vpaddd_s64 (int64x2_t a)
 {
   return vpaddd_s64 (a);
 }
 
+uint64_t
+test_vpaddd_u64 (uint64x2_t a)
+{
+  return vpaddd_u64 (a);
+}
+
 /* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */
 
 uint64_t
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
new file mode 100644
index 0000000..041da8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
@@ -0,0 +1,27 @@
+/* Test the vpaddd_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+float64_t in[SIZE] = { -4.0, 4.0, -2.0, 2.0, -1.0, 1.0 };
+
+int
+main (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 2; ++i)
+    if (vpaddd_f64 (vld1q_f64 (in + 2 * i)) != 0.0)
+      abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
new file mode 100644
index 0000000..44714d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
@@ -0,0 +1,27 @@
+/* Test the vpaddd_s64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+int64_t in[SIZE] = { -4l, 4l, -2l, 2l, -1l, 1l };
+
+int
+main (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 2; ++i)
+    if (vpaddd_s64 (vld1q_s64 (in + 2 * i)) != 0)
+      abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
new file mode 100644
index 0000000..013ca00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
@@ -0,0 +1,27 @@
+/* Test the vpaddd_u64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+uint64_t in[SIZE] = { 4ul, 4ul, 2ul, 2ul, 1ul, 1ul };
+
+int
+main (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 2; ++i)
+    if (vpaddd_u64 (vld1q_u64 (in + 2 * i)) != 2 * in[2 * i])
+      abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */