Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.

    gcc/
    * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
    * config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
    (with_fpu): Allow --with-fpu=neon.
    * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
    * config/arm/arm-protos.h (neon_immediate_valid_for_move)
    (neon_immediate_valid_for_logic, neon_output_logic_immediate)
    (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
    (neon_emit_pair_result_insn, neon_disambiguate_copy)
    (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
    (output_move_neon): Add prototypes.
    * config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
    (all_fpus): Add FPUTYPE_NEON.
    (fp_model_for_fpu): Add NEON field.
    (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
    (arm_arg_partial_bytes): Allow NEON vectors to be passed partially
    in registers.
    (arm_legitimate_address_p): Don't support fancy addressing for NEON
    structure moves.
    (thumb2_legitimate_address_p): Likewise.
    (neon_valid_immediate): Recognize and prepare constants suitable for
    NEON instructions.
    (neon_immediate_valid_for_move): New function. Recognize and prepare
    immediates for NEON move instructions.
    (neon_immediate_valid_for_logic): New function. Recognize and
    prepare immediates for NEON logic instructions.
    (neon_output_logic_immediate): New function. Create asm string
    suitable for outputting immediate logic instructions.
    (neon_pairwise_reduce): New function. Implement reduction using
    pairwise operations.
    (neon_expand_vector_init): New function. Expand a (possibly
    non-constant) vector initialization.
    (neon_vector_mem_operand): New function. Memory operands supported
    for quad-word loads/stores to/from ARM or NEON registers. Don't
    allow base+offset addressing for core regs.
    (neon_struct_mem_operand): New function. Valid mems for NEON
    structure moves.
    (coproc_secondary_reload_class): Enable NEON registers to be loaded
    from neon_vector_mem_operand addresses without a secondary register.
    (add_minipool_forward_ref): Handle >8-byte minipool entries.
    (add_minipool_backward_ref): Likewise.
    (dump_minipool): Likewise.
    (push_minipool_fix): Likewise.
    (output_move_quad): New function. Output quad-word moves, loads and
    stores using ARM registers.
    (output_move_vfp): Add support for vectors in VFP (NEON) D
    registers.
    (output_move_neon): Output a NEON load/store to/from a quadword
    register.
    (arm_print_operand): Implement new codes:
    - 'c' for unadorned integers (without a # sign).
    - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
    mode.
    - 'e', 'f' for the low and high D parts of a NEON Q register.
    - 'q' outputs a NEON Q register.
    - 'h' outputs ranges of D registers for VLDM/VSTM etc.
    - 'T' prints NEON opcode features from a coded bitmask.
    - 'F' is similar to T, but signed/unsigned codes both print as
    'i'.
    - 't' is similar to T, but 'u' is printed instead of 'p'.
    - 'O' prints 'r' if NEON instruction should perform rounding (as
    specified by bitmask), else prints nothing.
    - '#' is a punctuation character to stop operand numbers from
    running together with following digits in the assembler
    strings for instructions (when using mode attributes).
    (arm_assemble_integer): Handle extra NEON vector modes. Permute
    constant vectors in big-endian mode, where necessary.
    (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
    Handle EI, OI, CI, XI modes.
    (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
    (ashrv2si3): Rename IWMMXT2_BUILTINs to...
    (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
    (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
    (neon_builtin_type_bits): Add enumeration, one bit for each vector
    type.
    (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
    (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
    to turn v8qi, etc. into bits defined above.
    (neon_itype): New enumeration. Classifications of NEON builtins.
    (neon_builtin_datum): Define struct. Contains information about
    a single builtin (with multiple modes).
    (CF): Define helper macro for...
    (VAR1...VAR10): Define builtins with a type, name and 1-10 different
    modes.
    (neon_builtin_data): New array. Define information about builtins
    for use during initialization/expansion.
    (arm_init_neon_builtins): New function.
    (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
    true.
    (neon_builtin_compare): New function.
    (locate_neon_builtin_icode): New function. Find an insn code for a
    builtin given a function code for that builtin. Also return type of
    builtin (NEON_BINOP, NEON_UNOP etc.).
    (builtin_arg): New enumeration. Types of arguments for builtins.
    (arm_expand_neon_args): New function. Expand a generic NEON builtin.
    Takes a variable argument list of builtin_arg types, terminated by
    NEON_ARG_STOP.
    (arm_expand_neon_builtin): New function. Expand a NEON builtin.
    (neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
    (neon_emit_pair_result_insn): New function. Support returning pairs
    of vectors via a pointer.
    (neon_disambiguate_copy): New function. Set up operands for a
    multi-word copy such that registers do not get clobbered.
    (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
    ARM_BUILTIN_NEON_BASE.
    (arm_file_start): Set float-abi attribute for NEON.
    (arm_vector_mode_supported_p): Enable NEON vector modes.
    (arm_mangle_map_entry): New.
    (arm_mangle_map): New.
    (arm_mangle_vector_type): New.
    * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
    when appropriate.
    (TARGET_NEON): New macro. Target supports NEON.
    (fputype): Add FPUTYPE_NEON.
    (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
    for vectorization based on command-line arg.
    (NEON_REGNO_OK_FOR_NREGS): Define.
    (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
    (VALID_NEON_STRUCT_MODE): Define.
    (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
    (arm_builtins): Add ARM_BUILTIN_NEON_BASE.
    * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
    (consttable_16): Add pattern for outputting 16-byte minipool
    entries.
    (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
    vec-common.md).
    (vec-common.md, neon.md): Include md files.
    * config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
    * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
    (memory_constraint "Ut", "Un", "Us"): Define.
    * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
    (MMX_char): New mode attribute.
    (addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
    (*add<mode>3_iwmmxt): New insn pattern.
    (subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
    (*sub<mode>3_iwmmxt): New insn pattern.
    (mulv4hi3): Rename to...
    (*mulv4hi3_iwmmxt): This.
    (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
    (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
    (uminv4hi3, uminv2si3): Remove. Replace with...
    (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
    (*umin<mode>3_iwmmxt): These.
    (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
    (ashr<mode>3_iwmmxt): This new pattern.
    (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
    (lshr<mode>3_iwmmxt): This new pattern.
    (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
    (ashl<mode>3_iwmmxt): This new pattern.
    * config/arm/neon-docgen.ml: New file. Generate documentation for
    intrinsics.
    * config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
    * config/arm/arm_neon.h: New (autogenerated).
    * config/arm/neon-testgen.ml: New file. Generate NEON tests
    automatically.
    * config/arm/neon.md: New file. Define NEON instructions.
    * config/arm/neon.ml: New file. Abstract description of NEON
    instructions, used to generate arm_neon.h header, documentation and tests.
    * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
    * vec-common.md: New file. Shared parts for iWMMXt and NEON vector
    support.
    * doc/extend.texi (ARM Built-in Functions): Rename and remove
    extraneous comma.
    (ARM NEON Intrinsics): New subsection.
    * doc/arm-neon-intrinsics.texi: New (autogenerated).

    gcc/testsuite/
    * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
    * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
    * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
    * lib/target-supports.exp (check_effective_target_arm_neon_ok)
    (check_effective_target_arm_neon_hw): New.
    * gcc.target/arm/neon/neon.exp: New file.
    * gcc.target/arm/neon/polytypes.c: New file.
    * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).


Co-Authored-By: Joseph Myers <joseph@codesourcery.com>
Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com>
Co-Authored-By: Paul Brook <paul@codesourcery.com>

From-SVN: r126911

1878 files changed, 36495 insertions, 2 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6efbafe..80fe92f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2007-07-25  Julian Brown  <julian@codesourcery.com>
+	    Paul Brook  <paul@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+	    Mark Shinwell  <shinwell@codesourcery.com>
+
+	* gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
+	* gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
+	* lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
+	* lib/target-supports.exp (check_effective_target_arm_neon_ok)
+	(check_effective_target_arm_neon_hw): New.
+	* gcc.target/arm/neon/neon.exp: New file.
+	* gcc.target/arm/neon/polytypes.c: New file.
+	* gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).
+
 2007-07-25  Janis Johnson  <janis187@us.ibm.com>
 
 	* gcc.c-torture/unsorted/dump-noaddr.c: Reduce string length for
diff --git a/gcc/testsuite/g++.dg/abi/mangle-neon.C b/gcc/testsuite/g++.dg/abi/mangle-neon.C
new file mode 100644
index 0000000..9f88f8b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/mangle-neon.C
@@ -0,0 +1,47 @@
+// Test that ARM NEON vector types have their names mangled correctly. 
+
+// { dg-do compile }
+// { dg-require-effective-target arm_neon_ok }
+// { dg-options "-mfpu=neon -mfloat-abi=softfp" }
+
+#include <arm_neon.h>
+
+void f0 (int8x8_t a) {}
+void f1 (int16x4_t a) {}
+void f2 (int32x2_t a) {}
+void f3 (uint8x8_t a) {}
+void f4 (uint16x4_t a) {}
+void f5 (uint32x2_t a) {}
+void f6 (float32x2_t a) {}
+void f7 (poly8x8_t a) {}
+void f8 (poly16x4_t a) {}
+
+void f9 (int8x16_t a) {}
+void f10 (int16x8_t a) {}
+void f11 (int32x4_t a) {}
+void f12 (uint8x16_t a) {}
+void f13 (uint16x8_t a) {}
+void f14 (uint32x4_t a) {}
+void f15 (float32x4_t a) {}
+void f16 (poly8x16_t a) {}
+void f17 (poly16x8_t a) {}
+
+// { dg-final { scan-assembler "_Z2f015__simd64_int8_t:" } }
+// { dg-final { scan-assembler "_Z2f116__simd64_int16_t:" } }
+// { dg-final { scan-assembler "_Z2f216__simd64_int32_t:" } }
+// { dg-final { scan-assembler "_Z2f316__simd64_uint8_t:" } }
+// { dg-final { scan-assembler "_Z2f417__simd64_uint16_t:" } }
+// { dg-final { scan-assembler "_Z2f517__simd64_uint32_t:" } }
+// { dg-final { scan-assembler "_Z2f618__simd64_float32_t:" } }
+// { dg-final { scan-assembler "_Z2f716__simd64_poly8_t:" } }
+// { dg-final { scan-assembler "_Z2f817__simd64_poly16_t:" } }
+// { dg-final { scan-assembler "_Z2f916__simd128_int8_t:" } }
+// { dg-final { scan-assembler "_Z3f1017__simd128_int16_t:" } }
+// { dg-final { scan-assembler "_Z3f1117__simd128_int32_t:" } }
+// { dg-final { scan-assembler "_Z3f1217__simd128_uint8_t:" } }
+// { dg-final { scan-assembler "_Z3f1318__simd128_uint16_t:" } }
+// { dg-final { scan-assembler "_Z3f1418__simd128_uint32_t:" } }
+// { dg-final { scan-assembler "_Z3f1519__simd128_float32_t:" } }
+// { dg-final { scan-assembler "_Z3f1617__simd128_poly8_t:" } }
+// { dg-final { scan-assembler "_Z3f1718__simd128_poly16_t:" } }
+
diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h
index a2195a8..76e7ff4 100644
--- a/gcc/testsuite/gcc.dg/vect/tree-vect.h
+++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h
@@ -21,6 +21,18 @@ void check_vect (void)
   asm volatile (".byte 0xf2,0x0f,0x10,0xc0");
 #elif defined(__sparc__)
   asm volatile (".word\t0x81b007c0");
+#elif defined(__arm__)
+  {
+    /* On some processors without NEON support, this instruction may
+       be a no-op, on others it may trap, so check that it executes
+       correctly.  */
+    long long a = 0, b = 1;
+    asm ("vorr %P0, %P1, %P2"
+	 : "=w" (a)
+	 : "0" (a), "w" (b));
+    if (a != 1)
+      exit (0);
+  }
 #endif
   signal (SIGILL, SIG_DFL);
 }
diff --git a/gcc/testsuite/gcc.dg/vect/vect.exp b/gcc/testsuite/gcc.dg/vect/vect.exp
index 6ad377b..0a9ce6b 100644
--- a/gcc/testsuite/gcc.dg/vect/vect.exp
+++ b/gcc/testsuite/gcc.dg/vect/vect.exp
@@ -83,6 +83,13 @@ if [istarget "powerpc*-*-*"] {
     }
 } elseif [istarget "ia64-*-*"] {
     set dg-do-what-default run
+} elseif [is-effective-target arm_neon_ok] {
+    lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
+    if [is-effective-target arm_neon_hw] {
+      set dg-do-what-default run
+    } else {
+      set dg-do-what-default compile
+    }
 } else {
     return
 }
diff --git a/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc/testsuite/gcc.target/arm/neon/neon.exp
new file mode 100644
index 0000000..9d7fd2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/neon.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 1997, 2004, 2006 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc/testsuite/gcc.target/arm/neon/polytypes.c
new file mode 100644
index 0000000..9aca667
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/polytypes.c
@@ -0,0 +1,47 @@
+/* Check that NEON polynomial vector types are suitably incompatible with
+   integer vector types of the same layout.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */
+
+#include <arm_neon.h>
+
+void s64_8 (int8x8_t a) {}
+void u64_8 (uint8x8_t a) {}
+void p64_8 (poly8x8_t a) {}
+void s64_16 (int16x4_t a) {}
+void u64_16 (uint16x4_t a) {}
+void p64_16 (poly16x4_t a) {}
+
+void s128_8 (int8x16_t a) {}
+void u128_8 (uint8x16_t a) {}
+void p128_8 (poly8x16_t a) {}
+void s128_16 (int16x8_t a) {}
+void u128_16 (uint16x8_t a) {}
+void p128_16 (poly16x8_t a) {}
+
+void foo ()
+{
+  poly8x8_t v64_8;
+  poly16x4_t v64_16;
+  poly8x16_t v128_8;
+  poly16x8_t v128_16;
+
+  s64_8 (v64_8); /* { dg-error "use -flax-vector-conversions.*incompatible type for argument 1 of 's64_8'" } */
+  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+  p64_8 (v64_8);
+
+  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+  p64_16 (v64_16);
+
+  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+  p128_8 (v128_8);
+
+  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+  p128_16 (v128_16);
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
new file mode 100644
index 0000000..68834af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
new file mode 100644
index 0000000..afa4307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
new file mode 100644
index 0000000..efa777c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
new file mode 100644
index 0000000..2406ba6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
new file mode 100644
index 0000000..3266f8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
new file mode 100644
index 0000000..e77356f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
new file mode 100644
index 0000000..dae4fe9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
new file mode 100644
index 0000000..bcd72ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
new file mode 100644
index 0000000..0c5874e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
new file mode 100644
index 0000000..1752110
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
new file mode 100644
index 0000000..92fb399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
new file mode 100644
index 0000000..39a8e01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
new file mode 100644
index 0000000..2a301d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
new file mode 100644
index 0000000..91d6494
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
new file mode 100644
index 0000000..25703e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
new file mode 100644
index 0000000..b655963
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
new file mode 100644
index 0000000..7ab8d5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
new file mode 100644
index 0000000..8f1cae9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
new file mode 100644
index 0000000..81c79b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
new file mode 100644
index 0000000..a91618c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
new file mode 100644
index 0000000..f20de10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
new file mode 100644
index 0000000..4c63dc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
new file mode 100644
index 0000000..fe8981e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
new file mode 100644
index 0000000..cdb4c32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
new file mode 100644
index 0000000..8771504
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
new file mode 100644
index 0000000..6ab254e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
new file mode 100644
index 0000000..e331988
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
new file mode 100644
index 0000000..2ba12c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
new file mode 100644
index 0000000..360c0c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
new file mode 100644
index 0000000..a9b68eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
new file mode 100644
index 0000000..d493b44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
new file mode 100644
index 0000000..82edc7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
new file mode 100644
index 0000000..b821e2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
new file mode 100644
index 0000000..f609ce0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
new file mode 100644
index 0000000..3ea1a5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
new file mode 100644
index 0000000..e66dec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
new file mode 100644
index 0000000..8d4d23c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
new file mode 100644
index 0000000..3ac4b09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
new file mode 100644
index 0000000..2454b80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
new file mode 100644
index 0000000..8a8b351
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
new file mode 100644
index 0000000..1388e75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
new file mode 100644
index 0000000..0218268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
new file mode 100644
index 0000000..45be077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
new file mode 100644
index 0000000..1921daa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
new file mode 100644
index 0000000..8369afb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
new file mode 100644
index 0000000..3632be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
new file mode 100644
index 0000000..262783d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
new file mode 100644
index 0000000..ed48025
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
new file mode 100644
index 0000000..5e66caa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
new file mode 100644
index 0000000..720f9ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
new file mode 100644
index 0000000..864aa5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
new file mode 100644
index 0000000..a313892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
new file mode 100644
index 0000000..e95ef92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
new file mode 100644
index 0000000..09e3299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
new file mode 100644
index 0000000..548d89e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
new file mode 100644
index 0000000..9a67f2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
new file mode 100644
index 0000000..803eab0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
new file mode 100644
index 0000000..541528f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
new file mode 100644
index 0000000..26f4049
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
new file mode 100644
index 0000000..9d701f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
new file mode 100644
index 0000000..a3ff5f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
new file mode 100644
index 0000000..7830c43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
new file mode 100644
index 0000000..bd12da1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
new file mode 100644
index 0000000..928dcd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
new file mode 100644
index 0000000..e7b2d1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
new file mode 100644
index 0000000..dd3c115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
new file mode 100644
index 0000000..98944d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
new file mode 100644
index 0000000..187bbc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
new file mode 100644
index 0000000..56009bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
new file mode 100644
index 0000000..f7879db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
new file mode 100644
index 0000000..25d25d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
new file mode 100644
index 0000000..07f587a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
new file mode 100644
index 0000000..ec62a28f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
new file mode 100644
index 0000000..a049aab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
new file mode 100644
index 0000000..515bac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
new file mode 100644
index 0000000..0e52946
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
new file mode 100644
index 0000000..f4ec788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
new file mode 100644
index 0000000..1b41a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
new file mode 100644
index 0000000..e15a611
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
new file mode 100644
index 0000000..b14068a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
new file mode 100644
index 0000000..91a1582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
new file mode 100644
index 0000000..61642ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
new file mode 100644
index 0000000..2227524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
new file mode 100644
index 0000000..4e92d03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc/testsuite/gcc.target/arm/neon/vabals16.c
new file mode 100644
index 0000000..65f1b9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals16.c
@@ -0,0 +1,21 @@
+/* Test the `vabals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc/testsuite/gcc.target/arm/neon/vabals32.c
new file mode 100644
index 0000000..13a696b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals32.c
@@ -0,0 +1,21 @@
+/* Test the `vabals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc/testsuite/gcc.target/arm/neon/vabals8.c
new file mode 100644
index 0000000..c7275b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals8.c
@@ -0,0 +1,21 @@
+/* Test the `vabals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
new file mode 100644
index 0000000..0be2473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
new file mode 100644
index 0000000..508420b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
new file mode 100644
index 0000000..0580eb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc/testsuite/gcc.target/arm/neon/vabas16.c
new file mode 100644
index 0000000..4122be9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas16.c
@@ -0,0 +1,21 @@
+/* Test the `vabas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc/testsuite/gcc.target/arm/neon/vabas32.c
new file mode 100644
index 0000000..ca08986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas32.c
@@ -0,0 +1,21 @@
+/* Test the `vabas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc/testsuite/gcc.target/arm/neon/vabas8.c
new file mode 100644
index 0000000..e03f228
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas8.c
@@ -0,0 +1,21 @@
+/* Test the `vabas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc/testsuite/gcc.target/arm/neon/vabau16.c
new file mode 100644
index 0000000..f67beca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau16.c
@@ -0,0 +1,21 @@
+/* Test the `vabau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc/testsuite/gcc.target/arm/neon/vabau32.c
new file mode 100644
index 0000000..b57d1cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau32.c
@@ -0,0 +1,21 @@
+/* Test the `vabau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc/testsuite/gcc.target/arm/neon/vabau8.c
new file mode 100644
index 0000000..03ce666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau8.c
@@ -0,0 +1,21 @@
+/* Test the `vabau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
new file mode 100644
index 0000000..0cec309
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
new file mode 100644
index 0000000..cd7cedb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
new file mode 100644
index 0000000..06a2d6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
new file mode 100644
index 0000000..dc52032
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
new file mode 100644
index 0000000..72cfd3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
new file mode 100644
index 0000000..cd0c361
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
new file mode 100644
index 0000000..15afaa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
new file mode 100644
index 0000000..58465a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
new file mode 100644
index 0000000..a9c495d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
new file mode 100644
index 0000000..8f18947
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
new file mode 100644
index 0000000..1696bbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
new file mode 100644
index 0000000..cb26a67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
new file mode 100644
index 0000000..34541ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
new file mode 100644
index 0000000..b84a045
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc/testsuite/gcc.target/arm/neon/vabds16.c
new file mode 100644
index 0000000..209b6da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds16.c
@@ -0,0 +1,20 @@
+/* Test the `vabds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc/testsuite/gcc.target/arm/neon/vabds32.c
new file mode 100644
index 0000000..e7d5d40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds32.c
@@ -0,0 +1,20 @@
+/* Test the `vabds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc/testsuite/gcc.target/arm/neon/vabds8.c
new file mode 100644
index 0000000..aba2178
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds8.c
@@ -0,0 +1,20 @@
+/* Test the `vabds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
new file mode 100644
index 0000000..bbb779a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
new file mode 100644
index 0000000..d51068c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
new file mode 100644
index 0000000..066c655
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
new file mode 100644
index 0000000..137a568
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
new file mode 100644
index 0000000..47cf5a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
new file mode 100644
index 0000000..f775b5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
new file mode 100644
index 0000000..1312449
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
new file mode 100644
index 0000000..53d6c0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc/testsuite/gcc.target/arm/neon/vabss16.c
new file mode 100644
index 0000000..8f91a70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc/testsuite/gcc.target/arm/neon/vabss32.c
new file mode 100644
index 0000000..7503366
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc/testsuite/gcc.target/arm/neon/vabss8.c
new file mode 100644
index 0000000..c7e77f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
new file mode 100644
index 0000000..7a232f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
new file mode 100644
index 0000000..a034cfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
new file mode 100644
index 0000000..e99ddb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
new file mode 100644
index 0000000..381ce4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
new file mode 100644
index 0000000..28a2676
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
new file mode 100644
index 0000000..dd860af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
new file mode 100644
index 0000000..d04f606
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
new file mode 100644
index 0000000..ed5b54a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
new file mode 100644
index 0000000..94c27aa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
new file mode 100644
index 0000000..646674e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
new file mode 100644
index 0000000..1328a85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
new file mode 100644
index 0000000..7b54f15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
new file mode 100644
index 0000000..5bd6cc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
new file mode 100644
index 0000000..87661d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
new file mode 100644
index 0000000..db1860df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
new file mode 100644
index 0000000..461d4ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
new file mode 100644
index 0000000..042eb51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
new file mode 100644
index 0000000..b236425
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
new file mode 100644
index 0000000..b04da8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
new file mode 100644
index 0000000..813a871
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
new file mode 100644
index 0000000..9815f81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
new file mode 100644
index 0000000..269f1c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc/testsuite/gcc.target/arm/neon/vadds16.c
new file mode 100644
index 0000000..2cf2e53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc/testsuite/gcc.target/arm/neon/vadds32.c
new file mode 100644
index 0000000..a2ec121
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc/testsuite/gcc.target/arm/neon/vadds64.c
new file mode 100644
index 0000000..21a917d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc/testsuite/gcc.target/arm/neon/vadds8.c
new file mode 100644
index 0000000..a14e94b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
new file mode 100644
index 0000000..bcf484e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
new file mode 100644
index 0000000..d921476
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
new file mode 100644
index 0000000..6684785
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
new file mode 100644
index 0000000..c06ea4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
new file mode 100644
index 0000000..2ca47d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
new file mode 100644
index 0000000..87a8090
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
new file mode 100644
index 0000000..1ebe6a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
new file mode 100644
index 0000000..bfea209
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
new file mode 100644
index 0000000..7381719
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
new file mode 100644
index 0000000..f87802b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
new file mode 100644
index 0000000..b3778cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
new file mode 100644
index 0000000..b153d2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
new file mode 100644
index 0000000..6a804e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
new file mode 100644
index 0000000..bcc3c6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
new file mode 100644
index 0000000..4f1b03c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
new file mode 100644
index 0000000..3979f26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
new file mode 100644
index 0000000..cc523d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
new file mode 100644
index 0000000..84f0985
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc/testsuite/gcc.target/arm/neon/vands16.c
new file mode 100644
index 0000000..ee77d19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands16.c
@@ -0,0 +1,20 @@
+/* Test the `vands16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc/testsuite/gcc.target/arm/neon/vands32.c
new file mode 100644
index 0000000..26abfdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands32.c
@@ -0,0 +1,20 @@
+/* Test the `vands32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc/testsuite/gcc.target/arm/neon/vands64.c
new file mode 100644
index 0000000..5a680a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands64.c
@@ -0,0 +1,20 @@
+/* Test the `vands64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc/testsuite/gcc.target/arm/neon/vands8.c
new file mode 100644
index 0000000..6404bf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands8.c
@@ -0,0 +1,20 @@
+/* Test the `vands8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc/testsuite/gcc.target/arm/neon/vandu16.c
new file mode 100644
index 0000000..470c90f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc/testsuite/gcc.target/arm/neon/vandu32.c
new file mode 100644
index 0000000..f8369cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc/testsuite/gcc.target/arm/neon/vandu64.c
new file mode 100644
index 0000000..6c1c0ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc/testsuite/gcc.target/arm/neon/vandu8.c
new file mode 100644
index 0000000..fa4cfb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
new file mode 100644
index 0000000..2da6e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
new file mode 100644
index 0000000..0457f40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
new file mode 100644
index 0000000..22095cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
new file mode 100644
index 0000000..4baa0e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
new file mode 100644
index 0000000..4ae91ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
new file mode 100644
index 0000000..2c74f88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
new file mode 100644
index 0000000..61839b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
new file mode 100644
index 0000000..b39f91c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc/testsuite/gcc.target/arm/neon/vbics16.c
new file mode 100644
index 0000000..f8b5cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics16.c
@@ -0,0 +1,20 @@
+/* Test the `vbics16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc/testsuite/gcc.target/arm/neon/vbics32.c
new file mode 100644
index 0000000..63e854c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics32.c
@@ -0,0 +1,20 @@
+/* Test the `vbics32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc/testsuite/gcc.target/arm/neon/vbics64.c
new file mode 100644
index 0000000..10a0b5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics64.c
@@ -0,0 +1,20 @@
+/* Test the `vbics64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc/testsuite/gcc.target/arm/neon/vbics8.c
new file mode 100644
index 0000000..d1e6db5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics8.c
@@ -0,0 +1,20 @@
+/* Test the `vbics8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
new file mode 100644
index 0000000..c961e80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
new file mode 100644
index 0000000..8c95eb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
new file mode 100644
index 0000000..e777016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
new file mode 100644
index 0000000..c121432
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
new file mode 100644
index 0000000..76e5005
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
new file mode 100644
index 0000000..ba97cbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+  poly16x8_t arg2_poly16x8_t;
+
+  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
new file mode 100644
index 0000000..475739a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+  poly8x16_t arg2_poly8x16_t;
+
+  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
new file mode 100644
index 0000000..6780fda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
new file mode 100644
index 0000000..6f2835c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
new file mode 100644
index 0000000..017f073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+  int64x2_t arg2_int64x2_t;
+
+  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
new file mode 100644
index 0000000..e2ed402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
new file mode 100644
index 0000000..99d379c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
new file mode 100644
index 0000000..7fc71bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
new file mode 100644
index 0000000..89e19ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+  uint64x2_t arg2_uint64x2_t;
+
+  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
new file mode 100644
index 0000000..c2ea8dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
new file mode 100644
index 0000000..edbe7df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
new file mode 100644
index 0000000..bd02dac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+  poly16x4_t arg2_poly16x4_t;
+
+  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
new file mode 100644
index 0000000..2456c53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  poly8x8_t arg2_poly8x8_t;
+
+  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
new file mode 100644
index 0000000..f21d509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
new file mode 100644
index 0000000..81a7975
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
new file mode 100644
index 0000000..fd5e684
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+  int64x1_t arg2_int64x1_t;
+
+  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
new file mode 100644
index 0000000..1e7b39a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
new file mode 100644
index 0000000..8c6480f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
new file mode 100644
index 0000000..16938cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
new file mode 100644
index 0000000..1370691
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+  uint64x1_t arg2_uint64x1_t;
+
+  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
new file mode 100644
index 0000000..a3ab766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
new file mode 100644
index 0000000..667f0c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcageQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcageQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
new file mode 100644
index 0000000..58feead
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
new file mode 100644
index 0000000..6ef7e14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
new file mode 100644
index 0000000..a6bc406
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
new file mode 100644
index 0000000..b26f68d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
new file mode 100644
index 0000000..8a3b87d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcalef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcalef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
new file mode 100644
index 0000000..6bab9d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
new file mode 100644
index 0000000..7862aa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
new file mode 100644
index 0000000..f8666c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
new file mode 100644
index 0000000..5c7976c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
new file mode 100644
index 0000000..d072120
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
new file mode 100644
index 0000000..5e6e2a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
new file mode 100644
index 0000000..3b141ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
new file mode 100644
index 0000000..85a0d89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
new file mode 100644
index 0000000..20824d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
new file mode 100644
index 0000000..7a1bb25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
new file mode 100644
index 0000000..5f341e6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
new file mode 100644
index 0000000..8a94960
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
new file mode 100644
index 0000000..6bb3276
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
new file mode 100644
index 0000000..254cb07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
new file mode 100644
index 0000000..f54eb77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
new file mode 100644
index 0000000..f183aa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
new file mode 100644
index 0000000..2c15f6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
new file mode 100644
index 0000000..0491585
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
new file mode 100644
index 0000000..52d77b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
new file mode 100644
index 0000000..97c6ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
new file mode 100644
index 0000000..e0d3374
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
new file mode 100644
index 0000000..d655943
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
new file mode 100644
index 0000000..58887c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
new file mode 100644
index 0000000..af891ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
new file mode 100644
index 0000000..a42747c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
new file mode 100644
index 0000000..6b3e502
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc/testsuite/gcc.target/arm/neon/vcges16.c
new file mode 100644
index 0000000..7294f37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges16.c
@@ -0,0 +1,20 @@
+/* Test the `vcges16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc/testsuite/gcc.target/arm/neon/vcges32.c
new file mode 100644
index 0000000..3310b9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges32.c
@@ -0,0 +1,20 @@
+/* Test the `vcges32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc/testsuite/gcc.target/arm/neon/vcges8.c
new file mode 100644
index 0000000..d4f2b4e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges8.c
@@ -0,0 +1,20 @@
+/* Test the `vcges8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
new file mode 100644
index 0000000..1ddc763
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
new file mode 100644
index 0000000..dd18404
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
new file mode 100644
index 0000000..38484e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
new file mode 100644
index 0000000..2fecd4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
new file mode 100644
index 0000000..d6830cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
new file mode 100644
index 0000000..b6ad60d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
new file mode 100644
index 0000000..357e33e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
new file mode 100644
index 0000000..875e30f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
new file mode 100644
index 0000000..691a65d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
new file mode 100644
index 0000000..d5148f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
new file mode 100644
index 0000000..ea5a97d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
new file mode 100644
index 0000000..24ae89b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
new file mode 100644
index 0000000..b724e66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
new file mode 100644
index 0000000..9ab5955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
new file mode 100644
index 0000000..c13c5cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
new file mode 100644
index 0000000..a9e709d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
new file mode 100644
index 0000000..0c4a6aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
new file mode 100644
index 0000000..6adad81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
new file mode 100644
index 0000000..076ae2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
new file mode 100644
index 0000000..e0ac858
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
new file mode 100644
index 0000000..20fe30c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
new file mode 100644
index 0000000..8d26481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
new file mode 100644
index 0000000..6270781
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
new file mode 100644
index 0000000..38500e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc/testsuite/gcc.target/arm/neon/vclef32.c
new file mode 100644
index 0000000..02256e75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclef32.c
@@ -0,0 +1,20 @@
+/* Test the `vclef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc/testsuite/gcc.target/arm/neon/vcles16.c
new file mode 100644
index 0000000..029d2a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles16.c
@@ -0,0 +1,20 @@
+/* Test the `vcles16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc/testsuite/gcc.target/arm/neon/vcles32.c
new file mode 100644
index 0000000..f29b6ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles32.c
@@ -0,0 +1,20 @@
+/* Test the `vcles32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc/testsuite/gcc.target/arm/neon/vcles8.c
new file mode 100644
index 0000000..d3de08f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles8.c
@@ -0,0 +1,20 @@
+/* Test the `vcles8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
new file mode 100644
index 0000000..f6d8f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
new file mode 100644
index 0000000..85322203
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
new file mode 100644
index 0000000..6043941
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
new file mode 100644
index 0000000..34ab6f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
new file mode 100644
index 0000000..2db0d67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
new file mode 100644
index 0000000..191a2d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc/testsuite/gcc.target/arm/neon/vclss16.c
new file mode 100644
index 0000000..c765308
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss16.c
@@ -0,0 +1,19 @@
+/* Test the `vclss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc/testsuite/gcc.target/arm/neon/vclss32.c
new file mode 100644
index 0000000..1eae0d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss32.c
@@ -0,0 +1,19 @@
+/* Test the `vclss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc/testsuite/gcc.target/arm/neon/vclss8.c
new file mode 100644
index 0000000..9c405a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss8.c
@@ -0,0 +1,19 @@
+/* Test the `vclss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
new file mode 100644
index 0000000..7cdb46a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
new file mode 100644
index 0000000..e7bfb19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
new file mode 100644
index 0000000..abe15d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
new file mode 100644
index 0000000..209bdee6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
new file mode 100644
index 0000000..03d1abb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
new file mode 100644
index 0000000..221fe48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
new file mode 100644
index 0000000..69c63fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
new file mode 100644
index 0000000..ad0463b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc/testsuite/gcc.target/arm/neon/vclts16.c
new file mode 100644
index 0000000..65cf14e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts16.c
@@ -0,0 +1,20 @@
+/* Test the `vclts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc/testsuite/gcc.target/arm/neon/vclts32.c
new file mode 100644
index 0000000..a349dce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts32.c
@@ -0,0 +1,20 @@
+/* Test the `vclts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc/testsuite/gcc.target/arm/neon/vclts8.c
new file mode 100644
index 0000000..48f2bfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts8.c
@@ -0,0 +1,20 @@
+/* Test the `vclts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
new file mode 100644
index 0000000..b98f8bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
new file mode 100644
index 0000000..cd219eea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
new file mode 100644
index 0000000..88f66a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
new file mode 100644
index 0000000..11cb6c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
new file mode 100644
index 0000000..13ffe35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
new file mode 100644
index 0000000..8004005
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
new file mode 100644
index 0000000..23069ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
new file mode 100644
index 0000000..48d27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
new file mode 100644
index 0000000..f5249ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
new file mode 100644
index 0000000..004dce9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
new file mode 100644
index 0000000..5b650f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
new file mode 100644
index 0000000..460f1ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
new file mode 100644
index 0000000..90fb91b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
new file mode 100644
index 0000000..1b7fffc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
new file mode 100644
index 0000000..df256ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
new file mode 100644
index 0000000..5622ffc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
new file mode 100644
index 0000000..61d13f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
new file mode 100644
index 0000000..4a72cbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
new file mode 100644
index 0000000..39acf6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
new file mode 100644
index 0000000..cc51c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
@@ -0,0 +1,19 @@
+/* Test the `vcnts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcnts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
new file mode 100644
index 0000000..925f741
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
new file mode 100644
index 0000000..4e6236c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
new file mode 100644
index 0000000..5d966ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
new file mode 100644
index 0000000..4c5b7e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
new file mode 100644
index 0000000..066bd8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
new file mode 100644
index 0000000..e20b4c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
new file mode 100644
index 0000000..2a36c31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
new file mode 100644
index 0000000..16985c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
new file mode 100644
index 0000000..3a850b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
new file mode 100644
index 0000000..bf46899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
new file mode 100644
index 0000000..b9417c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
new file mode 100644
index 0000000..156b678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
new file mode 100644
index 0000000..bbd8878
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
new file mode 100644
index 0000000..3a90e4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
new file mode 100644
index 0000000..c91a1dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
new file mode 100644
index 0000000..912d19b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
new file mode 100644
index 0000000..18455b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
new file mode 100644
index 0000000..a46d2c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
new file mode 100644
index 0000000..eb13d08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
new file mode 100644
index 0000000..e7f78b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
new file mode 100644
index 0000000..5014d0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
new file mode 100644
index 0000000..917fe77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
new file mode 100644
index 0000000..d475618
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
new file mode 100644
index 0000000..90fbf2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
new file mode 100644
index 0000000..483d5a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
new file mode 100644
index 0000000..0f111f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_ns32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
new file mode 100644
index 0000000..4f2a407
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
new file mode 100644
index 0000000..bd81d8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
new file mode 100644
index 0000000..8ccf41e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
new file mode 100644
index 0000000..f6e7623
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
new file mode 100644
index 0000000..6d1eed6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
new file mode 100644
index 0000000..fee5b80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
new file mode 100644
index 0000000..24e1e5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
new file mode 100644
index 0000000..526b950
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_ns32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
new file mode 100644
index 0000000..059e3de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
new file mode 100644
index 0000000..fe71a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
new file mode 100644
index 0000000..d257a46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
new file mode 100644
index 0000000..e6b6d91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvts32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
new file mode 100644
index 0000000..6f331e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
new file mode 100644
index 0000000..30f8fee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
new file mode 100644
index 0000000..bc92357
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
new file mode 100644
index 0000000..edba0c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
new file mode 100644
index 0000000..b987ac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
new file mode 100644
index 0000000..1180bce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
new file mode 100644
index 0000000..568bf7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
new file mode 100644
index 0000000..114bf32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
new file mode 100644
index 0000000..73a173c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
new file mode 100644
index 0000000..1266c9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
new file mode 100644
index 0000000..ec7742f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
new file mode 100644
index 0000000..14b3d5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
new file mode 100644
index 0000000..c38959a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
new file mode 100644
index 0000000..6e3e726
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
new file mode 100644
index 0000000..647ff2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
new file mode 100644
index 0000000..1fb27ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
new file mode 100644
index 0000000..a0e8f7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
new file mode 100644
index 0000000..7147960
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
new file mode 100644
index 0000000..6f2aea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
new file mode 100644
index 0000000..bbf5020
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
new file mode 100644
index 0000000..e149335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
new file mode 100644
index 0000000..d989e6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
new file mode 100644
index 0000000..81cf626
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
new file mode 100644
index 0000000..4f21c51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
new file mode 100644
index 0000000..eba3a1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
new file mode 100644
index 0000000..90bdc97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
new file mode 100644
index 0000000..ee7f855
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
new file mode 100644
index 0000000..f162624
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
new file mode 100644
index 0000000..5d26382
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
new file mode 100644
index 0000000..8874bc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
new file mode 100644
index 0000000..244b5a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
new file mode 100644
index 0000000..8fd5c6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
new file mode 100644
index 0000000..5939b33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
new file mode 100644
index 0000000..2ba6a86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
new file mode 100644
index 0000000..277b200
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
new file mode 100644
index 0000000..76f1c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
new file mode 100644
index 0000000..ea66a60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
new file mode 100644
index 0000000..89794c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
new file mode 100644
index 0000000..8b0fed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
new file mode 100644
index 0000000..53b7121
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
new file mode 100644
index 0000000..0d39eec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
new file mode 100644
index 0000000..eb02c37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
new file mode 100644
index 0000000..84e8c76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
new file mode 100644
index 0000000..863fc78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
new file mode 100644
index 0000000..4d6ab33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
new file mode 100644
index 0000000..a2f4ece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
new file mode 100644
index 0000000..8f9cacb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
new file mode 100644
index 0000000..e50bd8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
new file mode 100644
index 0000000..be5c56b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
new file mode 100644
index 0000000..6ef6b6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
new file mode 100644
index 0000000..b95ac50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
new file mode 100644
index 0000000..f9f8b13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
new file mode 100644
index 0000000..4aa8567
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc/testsuite/gcc.target/arm/neon/veors16.c
new file mode 100644
index 0000000..d6e488f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors16.c
@@ -0,0 +1,20 @@
+/* Test the `veors16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc/testsuite/gcc.target/arm/neon/veors32.c
new file mode 100644
index 0000000..6b897db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors32.c
@@ -0,0 +1,20 @@
+/* Test the `veors32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc/testsuite/gcc.target/arm/neon/veors64.c
new file mode 100644
index 0000000..b82f054
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors64.c
@@ -0,0 +1,20 @@
+/* Test the `veors64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc/testsuite/gcc.target/arm/neon/veors8.c
new file mode 100644
index 0000000..8a33c1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors8.c
@@ -0,0 +1,20 @@
+/* Test the `veors8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc/testsuite/gcc.target/arm/neon/veoru16.c
new file mode 100644
index 0000000..418cf80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru16.c
@@ -0,0 +1,20 @@
+/* Test the `veoru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc/testsuite/gcc.target/arm/neon/veoru32.c
new file mode 100644
index 0000000..06f8437
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru32.c
@@ -0,0 +1,20 @@
+/* Test the `veoru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc/testsuite/gcc.target/arm/neon/veoru64.c
new file mode 100644
index 0000000..d73173e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru64.c
@@ -0,0 +1,20 @@
+/* Test the `veoru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc/testsuite/gcc.target/arm/neon/veoru8.c
new file mode 100644
index 0000000..87001b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru8.c
@@ -0,0 +1,20 @@
+/* Test the `veoru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
new file mode 100644
index 0000000..e7d67ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
new file mode 100644
index 0000000..8714a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
new file mode 100644
index 0000000..b33fbaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
new file mode 100644
index 0000000..81e157b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
new file mode 100644
index 0000000..bb964dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
new file mode 100644
index 0000000..dd57bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
new file mode 100644
index 0000000..2f334cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
new file mode 100644
index 0000000..de8d65a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
new file mode 100644
index 0000000..bac7395
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
new file mode 100644
index 0000000..31ef034
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
new file mode 100644
index 0000000..a894cce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc/testsuite/gcc.target/arm/neon/vextf32.c
new file mode 100644
index 0000000..53218b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc/testsuite/gcc.target/arm/neon/vextp16.c
new file mode 100644
index 0000000..a352a6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc/testsuite/gcc.target/arm/neon/vextp8.c
new file mode 100644
index 0000000..5465cc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc/testsuite/gcc.target/arm/neon/vexts16.c
new file mode 100644
index 0000000..0aa791b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts16.c
@@ -0,0 +1,20 @@
+/* Test the `vexts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc/testsuite/gcc.target/arm/neon/vexts32.c
new file mode 100644
index 0000000..1087e8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts32.c
@@ -0,0 +1,20 @@
+/* Test the `vexts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc/testsuite/gcc.target/arm/neon/vexts64.c
new file mode 100644
index 0000000..ca0256d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts64.c
@@ -0,0 +1,20 @@
+/* Test the `vexts64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc/testsuite/gcc.target/arm/neon/vexts8.c
new file mode 100644
index 0000000..145f809
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts8.c
@@ -0,0 +1,20 @@
+/* Test the `vexts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc/testsuite/gcc.target/arm/neon/vextu16.c
new file mode 100644
index 0000000..ca751ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc/testsuite/gcc.target/arm/neon/vextu32.c
new file mode 100644
index 0000000..4a3d01e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc/testsuite/gcc.target/arm/neon/vextu64.c
new file mode 100644
index 0000000..3f37d94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc/testsuite/gcc.target/arm/neon/vextu8.c
new file mode 100644
index 0000000..e2dcc59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
new file mode 100644
index 0000000..aa4dad6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
new file mode 100644
index 0000000..a18a384
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
new file mode 100644
index 0000000..2e6c7d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
new file mode 100644
index 0000000..f341ae0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
new file mode 100644
index 0000000..551fd28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
new file mode 100644
index 0000000..ec361e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
new file mode 100644
index 0000000..fa2726a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
new file mode 100644
index 0000000..2c2a9406
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
new file mode 100644
index 0000000..e919172
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
new file mode 100644
index 0000000..8cdab03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
new file mode 100644
index 0000000..df63fc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
new file mode 100644
index 0000000..5176c5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
new file mode 100644
index 0000000..e587008
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
new file mode 100644
index 0000000..0feab86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
new file mode 100644
index 0000000..786428a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
new file mode 100644
index 0000000..515ba13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
new file mode 100644
index 0000000..f191556
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
new file mode 100644
index 0000000..1c057b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
new file mode 100644
index 0000000..d3f0702
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
new file mode 100644
index 0000000..bd9cb4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
new file mode 100644
index 0000000..b791863
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
new file mode 100644
index 0000000..f8c804b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
new file mode 100644
index 0000000..3f0a027
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
new file mode 100644
index 0000000..22851e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
new file mode 100644
index 0000000..83c9a15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
new file mode 100644
index 0000000..d7feb6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
new file mode 100644
index 0000000..441b623
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
new file mode 100644
index 0000000..f70a477
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
new file mode 100644
index 0000000..86fcf63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
new file mode 100644
index 0000000..363fa2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
new file mode 100644
index 0000000..13d3380
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
new file mode 100644
index 0000000..3f18910
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
new file mode 100644
index 0000000..f244a75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
new file mode 100644
index 0000000..ae63430
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
new file mode 100644
index 0000000..c24ac0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
new file mode 100644
index 0000000..45d65bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
new file mode 100644
index 0000000..8e6c29a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
new file mode 100644
index 0000000..e018afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
new file mode 100644
index 0000000..e2e2bd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
new file mode 100644
index 0000000..0be24de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
new file mode 100644
index 0000000..67bcd50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
new file mode 100644
index 0000000..d21d97a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
new file mode 100644
index 0000000..79cf1c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
new file mode 100644
index 0000000..0399649
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
new file mode 100644
index 0000000..69e15af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
new file mode 100644
index 0000000..76f5c0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
new file mode 100644
index 0000000..403c77c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
new file mode 100644
index 0000000..aebfc02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
new file mode 100644
index 0000000..72f2373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
new file mode 100644
index 0000000..bcfe44c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
new file mode 100644
index 0000000..d412ccc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
new file mode 100644
index 0000000..db1749e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
new file mode 100644
index 0000000..086f569
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
new file mode 100644
index 0000000..1f230e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
new file mode 100644
index 0000000..fbdc8ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
new file mode 100644
index 0000000..38b82bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
new file mode 100644
index 0000000..df790e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
new file mode 100644
index 0000000..0442173
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
new file mode 100644
index 0000000..b98ada2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
new file mode 100644
index 0000000..b8ded58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
new file mode 100644
index 0000000..f8e2bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
new file mode 100644
index 0000000..b3ca8b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
new file mode 100644
index 0000000..841f9f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
new file mode 100644
index 0000000..8564c4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
new file mode 100644
index 0000000..7bd4ec3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
new file mode 100644
index 0000000..e5fab51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
new file mode 100644
index 0000000..ea6bf12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
new file mode 100644
index 0000000..d4569d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
new file mode 100644
index 0000000..0989045
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
new file mode 100644
index 0000000..ba9e56f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
new file mode 100644
index 0000000..b914ff2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
new file mode 100644
index 0000000..6be2a73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
new file mode 100644
index 0000000..37b47a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
new file mode 100644
index 0000000..a7199f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
new file mode 100644
index 0000000..b540c2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
new file mode 100644
index 0000000..23a6ade
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
new file mode 100644
index 0000000..4b8c2ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
new file mode 100644
index 0000000..7c1f803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
new file mode 100644
index 0000000..94e47c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
new file mode 100644
index 0000000..c1bd1d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
new file mode 100644
index 0000000..2c0a1a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
new file mode 100644
index 0000000..1719549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
new file mode 100644
index 0000000..9342b19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
new file mode 100644
index 0000000..3751aa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
new file mode 100644
index 0000000..b5fafa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
new file mode 100644
index 0000000..44c3917
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
new file mode 100644
index 0000000..19fd69f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
new file mode 100644
index 0000000..b66d4e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
new file mode 100644
index 0000000..ef77c5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
new file mode 100644
index 0000000..70f1b6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
new file mode 100644
index 0000000..d41bfc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
new file mode 100644
index 0000000..2be0749
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
new file mode 100644
index 0000000..f6ddd39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
new file mode 100644
index 0000000..790c371
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
new file mode 100644
index 0000000..66c28eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
new file mode 100644
index 0000000..4ee9145
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
new file mode 100644
index 0000000..28aad33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
new file mode 100644
index 0000000..cbf758c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
new file mode 100644
index 0000000..6f7c45aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
new file mode 100644
index 0000000..90a191b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
new file mode 100644
index 0000000..b55be21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
new file mode 100644
index 0000000..dc03801
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupf32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
new file mode 100644
index 0000000..cb87a39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
new file mode 100644
index 0000000..9dd5be3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
new file mode 100644
index 0000000..ca5b291
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
new file mode 100644
index 0000000..b565205
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
new file mode 100644
index 0000000..723ae79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
new file mode 100644
index 0000000..ca78ecf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
new file mode 100644
index 0000000..f6ffab6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
new file mode 100644
index 0000000..8a769b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
new file mode 100644
index 0000000..8108c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
new file mode 100644
index 0000000..dac97a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
new file mode 100644
index 0000000..512db1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
new file mode 100644
index 0000000..60abc9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
new file mode 100644
index 0000000..60b2f1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
new file mode 100644
index 0000000..25f07cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
new file mode 100644
index 0000000..a166c43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
new file mode 100644
index 0000000..09b658a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
new file mode 100644
index 0000000..12eb7a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
new file mode 100644
index 0000000..2295380
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
new file mode 100644
index 0000000..6c540e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
new file mode 100644
index 0000000..4507ae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
new file mode 100644
index 0000000..5dc352d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
new file mode 100644
index 0000000..6b49354
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1f32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
new file mode 100644
index 0000000..80c2240
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
new file mode 100644
index 0000000..588ee4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
new file mode 100644
index 0000000..cc8277b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
new file mode 100644
index 0000000..575bf39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
new file mode 100644
index 0000000..0af7c1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
new file mode 100644
index 0000000..d63836b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
new file mode 100644
index 0000000..6419661
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
new file mode 100644
index 0000000..20306f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
new file mode 100644
index 0000000..f992088
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
new file mode 100644
index 0000000..d8bac1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
new file mode 100644
index 0000000..c2c32cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanef32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
new file mode 100644
index 0000000..5b5dec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanep16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
new file mode 100644
index 0000000..4358269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
new file mode 100644
index 0000000..27c4ee8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
new file mode 100644
index 0000000..909df96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
new file mode 100644
index 0000000..72cdaa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
new file mode 100644
index 0000000..dcd895a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
new file mode 100644
index 0000000..96d74eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
new file mode 100644
index 0000000..6d51f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+
+  out_poly8x16x2_t = vld2q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
new file mode 100644
index 0000000..01c80a08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
new file mode 100644
index 0000000..cd1d22b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
new file mode 100644
index 0000000..b67f87a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+
+  out_int8x16x2_t = vld2q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
new file mode 100644
index 0000000..a5f7b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
new file mode 100644
index 0000000..9b4e1c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
new file mode 100644
index 0000000..952cf65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+
+  out_uint8x16x2_t = vld2q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
new file mode 100644
index 0000000..ffba7c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
new file mode 100644
index 0000000..1e40efc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
new file mode 100644
index 0000000..f33424f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
new file mode 100644
index 0000000..e647bab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
new file mode 100644
index 0000000..818a5bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
new file mode 100644
index 0000000..eaf82c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
new file mode 100644
index 0000000..4fb2095
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
new file mode 100644
index 0000000..3ffdc1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
new file mode 100644
index 0000000..bed506a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
new file mode 100644
index 0000000..5535a58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
new file mode 100644
index 0000000..6722bef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
new file mode 100644
index 0000000..1daf731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanef32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
new file mode 100644
index 0000000..5384d2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
new file mode 100644
index 0000000..f26b55f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
new file mode 100644
index 0000000..f959635
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
new file mode 100644
index 0000000..f3147c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
new file mode 100644
index 0000000..60de663
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
new file mode 100644
index 0000000..9f5fbb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
new file mode 100644
index 0000000..12425bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
new file mode 100644
index 0000000..2c6fb34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
new file mode 100644
index 0000000..f66cd94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2f32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
new file mode 100644
index 0000000..f01c101
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
new file mode 100644
index 0000000..972af50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
new file mode 100644
index 0000000..0c678bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
new file mode 100644
index 0000000..cc18c19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
new file mode 100644
index 0000000..4534bc46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
new file mode 100644
index 0000000..36f1803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
new file mode 100644
index 0000000..b1c7ab7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
new file mode 100644
index 0000000..3f01c26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
new file mode 100644
index 0000000..5f16b33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
new file mode 100644
index 0000000..9bdf75b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
new file mode 100644
index 0000000..dc02a4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanef32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
new file mode 100644
index 0000000..3013d93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanep16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
new file mode 100644
index 0000000..df71176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
new file mode 100644
index 0000000..fd1ceef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
new file mode 100644
index 0000000..fcf07f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
new file mode 100644
index 0000000..5f3e892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
new file mode 100644
index 0000000..97c499f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qf32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
new file mode 100644
index 0000000..14c202e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
new file mode 100644
index 0000000..d58ee32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp8 (void)
+{
+  poly8x16x3_t out_poly8x16x3_t;
+
+  out_poly8x16x3_t = vld3q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
new file mode 100644
index 0000000..6adc176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
new file mode 100644
index 0000000..92f191c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
new file mode 100644
index 0000000..a9de5d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs8 (void)
+{
+  int8x16x3_t out_int8x16x3_t;
+
+  out_int8x16x3_t = vld3q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
new file mode 100644
index 0000000..50c4d51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
new file mode 100644
index 0000000..6678a87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
new file mode 100644
index 0000000..6a97f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu8 (void)
+{
+  uint8x16x3_t out_uint8x16x3_t;
+
+  out_uint8x16x3_t = vld3q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
new file mode 100644
index 0000000..2bbf936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupf32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
new file mode 100644
index 0000000..3018884
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
new file mode 100644
index 0000000..76aba84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
new file mode 100644
index 0000000..08b7c09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
new file mode 100644
index 0000000..016ade4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
new file mode 100644
index 0000000..9292d59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
new file mode 100644
index 0000000..959ea3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
new file mode 100644
index 0000000..633fff5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
new file mode 100644
index 0000000..88133e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
new file mode 100644
index 0000000..3eb5024
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
new file mode 100644
index 0000000..b9a0d9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
new file mode 100644
index 0000000..30590ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanef32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
new file mode 100644
index 0000000..ea1d05e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
new file mode 100644
index 0000000..1f2674e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
new file mode 100644
index 0000000..076128c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
new file mode 100644
index 0000000..bd3b3d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
new file mode 100644
index 0000000..551cc39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
new file mode 100644
index 0000000..13855ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
new file mode 100644
index 0000000..c3b274a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
new file mode 100644
index 0000000..ddfabd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
new file mode 100644
index 0000000..7e52b37b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3f32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
new file mode 100644
index 0000000..123deeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
new file mode 100644
index 0000000..8fabf5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
new file mode 100644
index 0000000..2b7212e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
new file mode 100644
index 0000000..9dfc618
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
new file mode 100644
index 0000000..b4b4527
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
new file mode 100644
index 0000000..2526f19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
new file mode 100644
index 0000000..54ea8b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
new file mode 100644
index 0000000..d6ab84c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
new file mode 100644
index 0000000..f31c480
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
new file mode 100644
index 0000000..3a6f3cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
new file mode 100644
index 0000000..2d37f62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanef32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
new file mode 100644
index 0000000..5af87b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanep16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
new file mode 100644
index 0000000..355f112
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
new file mode 100644
index 0000000..d8908b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
new file mode 100644
index 0000000..1775085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
new file mode 100644
index 0000000..78ffe90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
new file mode 100644
index 0000000..4ebabb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qf32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
new file mode 100644
index 0000000..9f22715
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
new file mode 100644
index 0000000..b1ff160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp8 (void)
+{
+  poly8x16x4_t out_poly8x16x4_t;
+
+  out_poly8x16x4_t = vld4q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
new file mode 100644
index 0000000..2416bf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
new file mode 100644
index 0000000..29e68e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
new file mode 100644
index 0000000..8dc9938
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs8 (void)
+{
+  int8x16x4_t out_int8x16x4_t;
+
+  out_int8x16x4_t = vld4q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
new file mode 100644
index 0000000..d12817c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
new file mode 100644
index 0000000..4122cb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
new file mode 100644
index 0000000..bde9967
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu8 (void)
+{
+  uint8x16x4_t out_uint8x16x4_t;
+
+  out_uint8x16x4_t = vld4q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
new file mode 100644
index 0000000..b8e38be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupf32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
new file mode 100644
index 0000000..b5a9900
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
new file mode 100644
index 0000000..d85c252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
new file mode 100644
index 0000000..1b90af6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
new file mode 100644
index 0000000..bf448d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
new file mode 100644
index 0000000..9c14ca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
new file mode 100644
index 0000000..25f32d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
new file mode 100644
index 0000000..f2d714f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
new file mode 100644
index 0000000..88ad8ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
new file mode 100644
index 0000000..70186d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
new file mode 100644
index 0000000..c4332e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
new file mode 100644
index 0000000..88996ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanef32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
new file mode 100644
index 0000000..5c11a67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
new file mode 100644
index 0000000..2fdbbc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
new file mode 100644
index 0000000..370a256
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
new file mode 100644
index 0000000..b0baefd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
new file mode 100644
index 0000000..f3383ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
new file mode 100644
index 0000000..7cfddaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
new file mode 100644
index 0000000..3c9397d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
new file mode 100644
index 0000000..ef42968
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
new file mode 100644
index 0000000..04a40c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4f32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
new file mode 100644
index 0000000..7852b45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
new file mode 100644
index 0000000..a13719b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
new file mode 100644
index 0000000..bf50d09f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
new file mode 100644
index 0000000..eaea85c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
new file mode 100644
index 0000000..f3572a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
new file mode 100644
index 0000000..077650d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
new file mode 100644
index 0000000..7820fb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
new file mode 100644
index 0000000..32c8219
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
new file mode 100644
index 0000000..f8946a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
new file mode 100644
index 0000000..c66b105
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
new file mode 100644
index 0000000..8af37bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
new file mode 100644
index 0000000..8de8567
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
new file mode 100644
index 0000000..0fb3731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
new file mode 100644
index 0000000..b50939f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
new file mode 100644
index 0000000..bfa6394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
new file mode 100644
index 0000000..0ea042e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
new file mode 100644
index 0000000..7e53e62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
new file mode 100644
index 0000000..f668f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
new file mode 100644
index 0000000..94a6639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
new file mode 100644
index 0000000..4ffbdc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
new file mode 100644
index 0000000..b633aab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
new file mode 100644
index 0000000..60b058b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
new file mode 100644
index 0000000..0acc33a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
new file mode 100644
index 0000000..17a2ede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
new file mode 100644
index 0000000..3fe60ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
new file mode 100644
index 0000000..07c4138
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
new file mode 100644
index 0000000..7bec8e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
new file mode 100644
index 0000000..fb7b544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
new file mode 100644
index 0000000..be13f5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
new file mode 100644
index 0000000..1ab6fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
new file mode 100644
index 0000000..5039f21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc/testsuite/gcc.target/arm/neon/vminf32.c
new file mode 100644
index 0000000..4f4e772
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc/testsuite/gcc.target/arm/neon/vmins16.c
new file mode 100644
index 0000000..2ada1c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc/testsuite/gcc.target/arm/neon/vmins32.c
new file mode 100644
index 0000000..b0172fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc/testsuite/gcc.target/arm/neon/vmins8.c
new file mode 100644
index 0000000..99697d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc/testsuite/gcc.target/arm/neon/vminu16.c
new file mode 100644
index 0000000..62a8367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc/testsuite/gcc.target/arm/neon/vminu32.c
new file mode 100644
index 0000000..a6b3dd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc/testsuite/gcc.target/arm/neon/vminu8.c
new file mode 100644
index 0000000..e53ea9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
new file mode 100644
index 0000000..a8dc703
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
new file mode 100644
index 0000000..45735bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
new file mode 100644
index 0000000..4567e54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
new file mode 100644
index 0000000..2f816b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
new file mode 100644
index 0000000..e01352e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
new file mode 100644
index 0000000..39fb2303
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
new file mode 100644
index 0000000..54b5c86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
new file mode 100644
index 0000000..52c2191
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
new file mode 100644
index 0000000..2691478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
new file mode 100644
index 0000000..2ad903e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
new file mode 100644
index 0000000..207b330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
new file mode 100644
index 0000000..f8d3d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
new file mode 100644
index 0000000..5230048
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
new file mode 100644
index 0000000..1459774
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
new file mode 100644
index 0000000..82b5e44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
new file mode 100644
index 0000000..7b8bbed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
new file mode 100644
index 0000000..d6c22f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
new file mode 100644
index 0000000..6594789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
new file mode 100644
index 0000000..0b3b495
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
new file mode 100644
index 0000000..67c03f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
new file mode 100644
index 0000000..9a028e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
new file mode 100644
index 0000000..820410c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
new file mode 100644
index 0000000..b138b4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
new file mode 100644
index 0000000..79c8cd76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
new file mode 100644
index 0000000..af04a34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
new file mode 100644
index 0000000..66ed0b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
new file mode 100644
index 0000000..4574fbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
new file mode 100644
index 0000000..3da5485
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
new file mode 100644
index 0000000..d27decf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
new file mode 100644
index 0000000..67d8651
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
new file mode 100644
index 0000000..5645d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
new file mode 100644
index 0000000..6afa8e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
new file mode 100644
index 0000000..03e1f97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
new file mode 100644
index 0000000..9b76232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
new file mode 100644
index 0000000..7b423f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
new file mode 100644
index 0000000..4195d1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
new file mode 100644
index 0000000..d3ccb6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
new file mode 100644
index 0000000..257462e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
new file mode 100644
index 0000000..8be8a40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
new file mode 100644
index 0000000..614f314
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
new file mode 100644
index 0000000..6d7c9e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
new file mode 100644
index 0000000..fbb30c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
new file mode 100644
index 0000000..88630ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
new file mode 100644
index 0000000..281502d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
new file mode 100644
index 0000000..05e17f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
new file mode 100644
index 0000000..a39e61d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
new file mode 100644
index 0000000..35943a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
new file mode 100644
index 0000000..2876021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
new file mode 100644
index 0000000..e7b50dc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
new file mode 100644
index 0000000..6f33fb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
new file mode 100644
index 0000000..989f085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
new file mode 100644
index 0000000..f47f5d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
new file mode 100644
index 0000000..b1283eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
new file mode 100644
index 0000000..fd628ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
new file mode 100644
index 0000000..71d3ed7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
new file mode 100644
index 0000000..4a9d26c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
new file mode 100644
index 0000000..bbac90e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
new file mode 100644
index 0000000..dfd44ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
new file mode 100644
index 0000000..7670dd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
new file mode 100644
index 0000000..502647b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
new file mode 100644
index 0000000..9a7cd05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
new file mode 100644
index 0000000..5516a56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
new file mode 100644
index 0000000..4a6109a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
new file mode 100644
index 0000000..1e5192d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
new file mode 100644
index 0000000..1d92cf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
new file mode 100644
index 0000000..6e7acc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
new file mode 100644
index 0000000..35c4f65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
new file mode 100644
index 0000000..6bac7348
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
new file mode 100644
index 0000000..4a3e246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
new file mode 100644
index 0000000..c20cbd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
new file mode 100644
index 0000000..7567a17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
new file mode 100644
index 0000000..ebc4c9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
new file mode 100644
index 0000000..7dec64d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
new file mode 100644
index 0000000..3ef90d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
new file mode 100644
index 0000000..9716ede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
new file mode 100644
index 0000000..5c37698
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
new file mode 100644
index 0000000..306111b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
new file mode 100644
index 0000000..c366755
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
new file mode 100644
index 0000000..bf239d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
new file mode 100644
index 0000000..8a4b82a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
new file mode 100644
index 0000000..ab0feb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
new file mode 100644
index 0000000..685e017
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
new file mode 100644
index 0000000..63fe4a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
new file mode 100644
index 0000000..ad7ff60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
new file mode 100644
index 0000000..86b4981
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
new file mode 100644
index 0000000..9e399e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
new file mode 100644
index 0000000..a5fd648
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
new file mode 100644
index 0000000..95f8f15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
new file mode 100644
index 0000000..7bdbdcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
new file mode 100644
index 0000000..64ab744
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
new file mode 100644
index 0000000..9f05cbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
new file mode 100644
index 0000000..19a701e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
new file mode 100644
index 0000000..4e449c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
new file mode 100644
index 0000000..edf534b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
new file mode 100644
index 0000000..8d0e65a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
new file mode 100644
index 0000000..cc77dd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
new file mode 100644
index 0000000..7776b34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
new file mode 100644
index 0000000..72fbeda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
new file mode 100644
index 0000000..d908658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
new file mode 100644
index 0000000..77a2a41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
new file mode 100644
index 0000000..13ba030
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
new file mode 100644
index 0000000..7141de1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
new file mode 100644
index 0000000..999d709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
new file mode 100644
index 0000000..f02aca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
new file mode 100644
index 0000000..3c01d39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
new file mode 100644
index 0000000..84a4b04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
new file mode 100644
index 0000000..3013619
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
new file mode 100644
index 0000000..88fa47b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
new file mode 100644
index 0000000..5a726bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
new file mode 100644
index 0000000..d49655c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
new file mode 100644
index 0000000..faa4d54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
new file mode 100644
index 0000000..9f31a5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
new file mode 100644
index 0000000..c57a0a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
new file mode 100644
index 0000000..f68b01b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
new file mode 100644
index 0000000..a6053eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
new file mode 100644
index 0000000..9f0634e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
new file mode 100644
index 0000000..6d6d7c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
new file mode 100644
index 0000000..62f9d4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
new file mode 100644
index 0000000..08f4a4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
new file mode 100644
index 0000000..69d6cc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
new file mode 100644
index 0000000..6619eb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
new file mode 100644
index 0000000..50978bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
new file mode 100644
index 0000000..190fc0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
new file mode 100644
index 0000000..b8483e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
new file mode 100644
index 0000000..9ce728e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
new file mode 100644
index 0000000..e5d6ca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
new file mode 100644
index 0000000..5030a42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
new file mode 100644
index 0000000..85de70c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
new file mode 100644
index 0000000..72577c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
new file mode 100644
index 0000000..96ada07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
new file mode 100644
index 0000000..c06916f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
new file mode 100644
index 0000000..82b4c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
new file mode 100644
index 0000000..a4a4269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
new file mode 100644
index 0000000..aa8e337
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
new file mode 100644
index 0000000..04f060f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
new file mode 100644
index 0000000..ff3f18a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32_t arg1_float32_t;
+
+  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
new file mode 100644
index 0000000..7db9c73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
new file mode 100644
index 0000000..cc46dc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
new file mode 100644
index 0000000..bff5501
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
new file mode 100644
index 0000000..9ab5bf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
new file mode 100644
index 0000000..6cd7868
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
new file mode 100644
index 0000000..b46627c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
new file mode 100644
index 0000000..e83d127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
new file mode 100644
index 0000000..2828085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
new file mode 100644
index 0000000..ddc36f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
new file mode 100644
index 0000000..b5aceec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
new file mode 100644
index 0000000..4926b5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
new file mode 100644
index 0000000..431540f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
new file mode 100644
index 0000000..d5761b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
new file mode 100644
index 0000000..63f91aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
new file mode 100644
index 0000000..34c9964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
new file mode 100644
index 0000000..acca1fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
new file mode 100644
index 0000000..712b273
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
new file mode 100644
index 0000000..b2353e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32_t arg1_float32_t;
+
+  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
new file mode 100644
index 0000000..1be1ac5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
new file mode 100644
index 0000000..8ff82bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
new file mode 100644
index 0000000..4821925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
new file mode 100644
index 0000000..e55330a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
new file mode 100644
index 0000000..b2078b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
new file mode 100644
index 0000000..2f6cabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
new file mode 100644
index 0000000..711bc3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
new file mode 100644
index 0000000..31151a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
new file mode 100644
index 0000000..be4b6b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
new file mode 100644
index 0000000..6b7f080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
new file mode 100644
index 0000000..19a24d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
new file mode 100644
index 0000000..32a22ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
new file mode 100644
index 0000000..80ba521
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
new file mode 100644
index 0000000..849537e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullp8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
new file mode 100644
index 0000000..84f8abc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
new file mode 100644
index 0000000..38ca3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
new file mode 100644
index 0000000..c865208
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
new file mode 100644
index 0000000..1ff7232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
new file mode 100644
index 0000000..39f9102
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
new file mode 100644
index 0000000..679395e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
new file mode 100644
index 0000000..2ec17dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
new file mode 100644
index 0000000..1fb5047
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
new file mode 100644
index 0000000..2724c389
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
new file mode 100644
index 0000000..79de6b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
new file mode 100644
index 0000000..8c8aeff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
new file mode 100644
index 0000000..c00bb00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
new file mode 100644
index 0000000..a6349f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
new file mode 100644
index 0000000..82a1598
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
new file mode 100644
index 0000000..32fff2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
new file mode 100644
index 0000000..9dea79d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
new file mode 100644
index 0000000..2233671
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
new file mode 100644
index 0000000..7517830
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
new file mode 100644
index 0000000..58ebc8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
new file mode 100644
index 0000000..5cb87429
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
new file mode 100644
index 0000000..56e0190
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
new file mode 100644
index 0000000..d543e34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
new file mode 100644
index 0000000..03b8999
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
new file mode 100644
index 0000000..8e368e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
new file mode 100644
index 0000000..25209de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
new file mode 100644
index 0000000..9a81332
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
new file mode 100644
index 0000000..0668576
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
new file mode 100644
index 0000000..203232d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
new file mode 100644
index 0000000..dbe9277
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
new file mode 100644
index 0000000..6f1d81c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
new file mode 100644
index 0000000..88ae9eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
new file mode 100644
index 0000000..3083457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
new file mode 100644
index 0000000..bf7e9fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
new file mode 100644
index 0000000..e0cae01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
new file mode 100644
index 0000000..242174c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
new file mode 100644
index 0000000..3a5a97f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
new file mode 100644
index 0000000..ade7134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
new file mode 100644
index 0000000..da1e062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
new file mode 100644
index 0000000..d585a1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
new file mode 100644
index 0000000..b6f38e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
new file mode 100644
index 0000000..5904f8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
new file mode 100644
index 0000000..ff977d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
new file mode 100644
index 0000000..f60434b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc/testsuite/gcc.target/arm/neon/vorns16.c
new file mode 100644
index 0000000..eb26f74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns16.c
@@ -0,0 +1,20 @@
+/* Test the `vorns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc/testsuite/gcc.target/arm/neon/vorns32.c
new file mode 100644
index 0000000..de81c79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns32.c
@@ -0,0 +1,20 @@
+/* Test the `vorns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc/testsuite/gcc.target/arm/neon/vorns64.c
new file mode 100644
index 0000000..6e8b8e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns64.c
@@ -0,0 +1,20 @@
+/* Test the `vorns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc/testsuite/gcc.target/arm/neon/vorns8.c
new file mode 100644
index 0000000..dfb7730
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns8.c
@@ -0,0 +1,20 @@
+/* Test the `vorns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc/testsuite/gcc.target/arm/neon/vornu16.c
new file mode 100644
index 0000000..8575f9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc/testsuite/gcc.target/arm/neon/vornu32.c
new file mode 100644
index 0000000..02bac35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc/testsuite/gcc.target/arm/neon/vornu64.c
new file mode 100644
index 0000000..ce66653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc/testsuite/gcc.target/arm/neon/vornu8.c
new file mode 100644
index 0000000..4e3c593
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
new file mode 100644
index 0000000..428f30c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
new file mode 100644
index 0000000..787a618
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
new file mode 100644
index 0000000..73ff15f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
new file mode 100644
index 0000000..2234199
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
new file mode 100644
index 0000000..5b074ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
new file mode 100644
index 0000000..5543403
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
new file mode 100644
index 0000000..4b09979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
new file mode 100644
index 0000000..6795563
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
new file mode 100644
index 0000000..6f5d139
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
new file mode 100644
index 0000000..3410bc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
new file mode 100644
index 0000000..5372542
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
new file mode 100644
index 0000000..be6136c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc/testsuite/gcc.target/arm/neon/vorru16.c
new file mode 100644
index 0000000..ffd2b40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru16.c
@@ -0,0 +1,20 @@
+/* Test the `vorru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc/testsuite/gcc.target/arm/neon/vorru32.c
new file mode 100644
index 0000000..f7688ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru32.c
@@ -0,0 +1,20 @@
+/* Test the `vorru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc/testsuite/gcc.target/arm/neon/vorru64.c
new file mode 100644
index 0000000..cf8352f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru64.c
@@ -0,0 +1,20 @@
+/* Test the `vorru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc/testsuite/gcc.target/arm/neon/vorru8.c
new file mode 100644
index 0000000..c80b2e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru8.c
@@ -0,0 +1,20 @@
+/* Test the `vorru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
new file mode 100644
index 0000000..c7cc96f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
new file mode 100644
index 0000000..5051917
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
new file mode 100644
index 0000000..631e315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
new file mode 100644
index 0000000..dbe27b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
new file mode 100644
index 0000000..fb13006
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
new file mode 100644
index 0000000..044ac04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
new file mode 100644
index 0000000..130c63c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
new file mode 100644
index 0000000..73f8d1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
new file mode 100644
index 0000000..54f04c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
new file mode 100644
index 0000000..e1e186e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
new file mode 100644
index 0000000..44f1f26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
new file mode 100644
index 0000000..e4a4a18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
new file mode 100644
index 0000000..7e999dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
new file mode 100644
index 0000000..ee4590b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
new file mode 100644
index 0000000..63f2f00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
new file mode 100644
index 0000000..fde7218
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
new file mode 100644
index 0000000..7bbff20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
new file mode 100644
index 0000000..0d707a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
new file mode 100644
index 0000000..7ec49a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
new file mode 100644
index 0000000..2cf1f20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
new file mode 100644
index 0000000..990f9ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
new file mode 100644
index 0000000..31aaec3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
new file mode 100644
index 0000000..eda1abd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
new file mode 100644
index 0000000..dfd53c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
new file mode 100644
index 0000000..405b00f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
new file mode 100644
index 0000000..008762d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
new file mode 100644
index 0000000..03deb9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
new file mode 100644
index 0000000..49a4700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
new file mode 100644
index 0000000..d9e9b80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
new file mode 100644
index 0000000..5452e64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
new file mode 100644
index 0000000..fe967a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
new file mode 100644
index 0000000..fe8c167
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
new file mode 100644
index 0000000..26effea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
new file mode 100644
index 0000000..ca26dee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
new file mode 100644
index 0000000..6b6fab5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
new file mode 100644
index 0000000..c498274
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
new file mode 100644
index 0000000..e2218c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
new file mode 100644
index 0000000..20da629
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
new file mode 100644
index 0000000..0952bdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
new file mode 100644
index 0000000..fcf8e1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
new file mode 100644
index 0000000..0ca2213
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
new file mode 100644
index 0000000..b103cb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
new file mode 100644
index 0000000..f214791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
new file mode 100644
index 0000000..5dcc5a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
new file mode 100644
index 0000000..f2627fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
new file mode 100644
index 0000000..e0a48af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
new file mode 100644
index 0000000..c82b8a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
new file mode 100644
index 0000000..410d291
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
new file mode 100644
index 0000000..512a643
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
new file mode 100644
index 0000000..e841e0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
new file mode 100644
index 0000000..e694c4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
new file mode 100644
index 0000000..57aa085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
new file mode 100644
index 0000000..910b082
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
new file mode 100644
index 0000000..f2e1c2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
new file mode 100644
index 0000000..736e3d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
new file mode 100644
index 0000000..ce7542a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
new file mode 100644
index 0000000..00b054c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
new file mode 100644
index 0000000..daa4f3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
new file mode 100644
index 0000000..08afba1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
new file mode 100644
index 0000000..af2a366
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
new file mode 100644
index 0000000..92cb8f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
new file mode 100644
index 0000000..534d6ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
new file mode 100644
index 0000000..fa08499
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
new file mode 100644
index 0000000..8f5d5fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
new file mode 100644
index 0000000..4c2b7d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
new file mode 100644
index 0000000..c6fa26e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
new file mode 100644
index 0000000..3d5e013
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
new file mode 100644
index 0000000..ea48f7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
new file mode 100644
index 0000000..f2fdc51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
new file mode 100644
index 0000000..49c6ffd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
new file mode 100644
index 0000000..7475bf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
new file mode 100644
index 0000000..20064fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
new file mode 100644
index 0000000..24fd9de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
new file mode 100644
index 0000000..740c885
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
new file mode 100644
index 0000000..1fc90b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
new file mode 100644
index 0000000..4b34127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
new file mode 100644
index 0000000..be40d43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
new file mode 100644
index 0000000..8870855
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
new file mode 100644
index 0000000..41898b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
new file mode 100644
index 0000000..85a7e10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
new file mode 100644
index 0000000..ffd2053
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
new file mode 100644
index 0000000..bb47b08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
new file mode 100644
index 0000000..5d230ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
new file mode 100644
index 0000000..a5ef813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
new file mode 100644
index 0000000..9f3a4c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
new file mode 100644
index 0000000..597e20f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
new file mode 100644
index 0000000..9585874
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
new file mode 100644
index 0000000..086ff49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
new file mode 100644
index 0000000..649a704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
new file mode 100644
index 0000000..3c80d27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
new file mode 100644
index 0000000..fd46551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
new file mode 100644
index 0000000..583439e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
new file mode 100644
index 0000000..3b1a874
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
new file mode 100644
index 0000000..c4e22fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
new file mode 100644
index 0000000..80ad826
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
new file mode 100644
index 0000000..c9ec1a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
new file mode 100644
index 0000000..b8d9e8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
new file mode 100644
index 0000000..1cb7d2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
new file mode 100644
index 0000000..fd0a401
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
new file mode 100644
index 0000000..b64cbf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
new file mode 100644
index 0000000..41664ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
new file mode 100644
index 0000000..3fdeeba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
new file mode 100644
index 0000000..7a48092
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
new file mode 100644
index 0000000..ceb70e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
new file mode 100644
index 0000000..02e5b0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
new file mode 100644
index 0000000..9256224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
new file mode 100644
index 0000000..24ce983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
new file mode 100644
index 0000000..885fecc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
new file mode 100644
index 0000000..a1bdf95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
new file mode 100644
index 0000000..ac858e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
new file mode 100644
index 0000000..bba7153
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
new file mode 100644
index 0000000..2c11814
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
new file mode 100644
index 0000000..56da4c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
new file mode 100644
index 0000000..dad599d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
new file mode 100644
index 0000000..80ea5ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
new file mode 100644
index 0000000..daf9a6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
new file mode 100644
index 0000000..9c56512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
new file mode 100644
index 0000000..e5a0bf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
new file mode 100644
index 0000000..7ae3a22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
new file mode 100644
index 0000000..e742ff5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
new file mode 100644
index 0000000..75b7951
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
new file mode 100644
index 0000000..b9a19ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
new file mode 100644
index 0000000..597032f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
new file mode 100644
index 0000000..1314664
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
new file mode 100644
index 0000000..537be4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
new file mode 100644
index 0000000..407e616
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
new file mode 100644
index 0000000..20c1611
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
new file mode 100644
index 0000000..3e76e8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
new file mode 100644
index 0000000..69309b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
new file mode 100644
index 0000000..ffa26d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
new file mode 100644
index 0000000..032a9a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
new file mode 100644
index 0000000..02eec1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
new file mode 100644
index 0000000..e3224c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
new file mode 100644
index 0000000..7c30698
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
new file mode 100644
index 0000000..49d103a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
new file mode 100644
index 0000000..ed48f20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
new file mode 100644
index 0000000..f3e2348
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
new file mode 100644
index 0000000..5ee9b9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
new file mode 100644
index 0000000..7bdfb5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
new file mode 100644
index 0000000..93c6eb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
new file mode 100644
index 0000000..3a92133d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
new file mode 100644
index 0000000..be303c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
new file mode 100644
index 0000000..660ac6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
new file mode 100644
index 0000000..eb5ac37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
new file mode 100644
index 0000000..d84a5fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
new file mode 100644
index 0000000..3907ccd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
new file mode 100644
index 0000000..2d9d99b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
new file mode 100644
index 0000000..e68a827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
new file mode 100644
index 0000000..7031200
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
new file mode 100644
index 0000000..75e9cc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
new file mode 100644
index 0000000..4b5933a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
new file mode 100644
index 0000000..1b56280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
new file mode 100644
index 0000000..31cf319
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
new file mode 100644
index 0000000..56101c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
new file mode 100644
index 0000000..1077566
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
new file mode 100644
index 0000000..d199c1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
new file mode 100644
index 0000000..55510f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
new file mode 100644
index 0000000..b4e8a5e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
new file mode 100644
index 0000000..200e2c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
new file mode 100644
index 0000000..8379c25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
new file mode 100644
index 0000000..1804b81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
new file mode 100644
index 0000000..14f5362
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
new file mode 100644
index 0000000..344e654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
new file mode 100644
index 0000000..bbc4efe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
new file mode 100644
index 0000000..69eb05f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
new file mode 100644
index 0000000..7992aaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
new file mode 100644
index 0000000..c7e5b8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
new file mode 100644
index 0000000..f5de910
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
new file mode 100644
index 0000000..70d0683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
new file mode 100644
index 0000000..9a06108
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
new file mode 100644
index 0000000..85f231c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
new file mode 100644
index 0000000..b91be64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
new file mode 100644
index 0000000..71b86c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
new file mode 100644
index 0000000..45ff5de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
new file mode 100644
index 0000000..f4ee413
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
new file mode 100644
index 0000000..590aa7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
new file mode 100644
index 0000000..a42fe15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
new file mode 100644
index 0000000..ca5c1a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
new file mode 100644
index 0000000..0ad2e72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
new file mode 100644
index 0000000..18b5a79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
new file mode 100644
index 0000000..ac6a2fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
new file mode 100644
index 0000000..2cb5910
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
new file mode 100644
index 0000000..d27c3e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
new file mode 100644
index 0000000..c8d3972
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
new file mode 100644
index 0000000..7edcd39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
new file mode 100644
index 0000000..bf439ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
new file mode 100644
index 0000000..e91e9fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
new file mode 100644
index 0000000..10ff898
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
new file mode 100644
index 0000000..0bcb604
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
new file mode 100644
index 0000000..5453979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
new file mode 100644
index 0000000..69c17e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
new file mode 100644
index 0000000..71f1cf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
new file mode 100644
index 0000000..59da1e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
new file mode 100644
index 0000000..23b03ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
new file mode 100644
index 0000000..7cf626a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
new file mode 100644
index 0000000..18943f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
new file mode 100644
index 0000000..705b314
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
new file mode 100644
index 0000000..097d4d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
new file mode 100644
index 0000000..c270c66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
new file mode 100644
index 0000000..e319ba2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
new file mode 100644
index 0000000..0b718f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
new file mode 100644
index 0000000..fc1aba4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
new file mode 100644
index 0000000..0e12019
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
new file mode 100644
index 0000000..30c5aec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
new file mode 100644
index 0000000..ee09535
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
new file mode 100644
index 0000000..506c444
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
new file mode 100644
index 0000000..f6b70bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
new file mode 100644
index 0000000..0ddfe5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
new file mode 100644
index 0000000..ad2c75f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
new file mode 100644
index 0000000..b39ed08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
new file mode 100644
index 0000000..d19df3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
new file mode 100644
index 0000000..50c298f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
new file mode 100644
index 0000000..77faa60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
new file mode 100644
index 0000000..a3cdcc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
new file mode 100644
index 0000000..d1010bca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
new file mode 100644
index 0000000..35a2588
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
new file mode 100644
index 0000000..f296b95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
new file mode 100644
index 0000000..3e57d35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
new file mode 100644
index 0000000..213021c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
new file mode 100644
index 0000000..6e7e419
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
new file mode 100644
index 0000000..998c3f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p16 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
new file mode 100644
index 0000000..c68861c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p8 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
new file mode 100644
index 0000000..99548c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s16 (void)
+{
+  float32x4_t out_float32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
new file mode 100644
index 0000000..13ce5b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
new file mode 100644
index 0000000..6cb0d85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s64 (void)
+{
+  float32x4_t out_float32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
new file mode 100644
index 0000000..a0b01cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s8 (void)
+{
+  float32x4_t out_float32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
new file mode 100644
index 0000000..b1ef77d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u16 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
new file mode 100644
index 0000000..bde7baf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
new file mode 100644
index 0000000..a72ed95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u64 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
new file mode 100644
index 0000000..e77bb98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u8 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
new file mode 100644
index 0000000..019cf58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_f32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
new file mode 100644
index 0000000..1b51eec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
new file mode 100644
index 0000000..8ae9b9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
new file mode 100644
index 0000000..09f2264
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
new file mode 100644
index 0000000..f7c7af0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
new file mode 100644
index 0000000..1727461
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
new file mode 100644
index 0000000..23c0f99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
new file mode 100644
index 0000000..ad21895
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
new file mode 100644
index 0000000..72b5f25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
new file mode 100644
index 0000000..ce056f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
new file mode 100644
index 0000000..ffe9956
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_f32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
new file mode 100644
index 0000000..f02d282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
new file mode 100644
index 0000000..dbbf983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
new file mode 100644
index 0000000..2881005
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
new file mode 100644
index 0000000..2e02423
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
new file mode 100644
index 0000000..61bbc85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
new file mode 100644
index 0000000..0b98d6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
new file mode 100644
index 0000000..aab2dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
new file mode 100644
index 0000000..9c1a59a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
new file mode 100644
index 0000000..8674e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
new file mode 100644
index 0000000..8f06678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_f32 (void)
+{
+  int16x8_t out_int16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
new file mode 100644
index 0000000..8a7a8f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p16 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
new file mode 100644
index 0000000..e14288d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p8 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
new file mode 100644
index 0000000..911c95e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s32 (void)
+{
+  int16x8_t out_int16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
new file mode 100644
index 0000000..86eaf66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s64 (void)
+{
+  int16x8_t out_int16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
new file mode 100644
index 0000000..baa8ee2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
new file mode 100644
index 0000000..436f9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
new file mode 100644
index 0000000..a7bd6f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u32 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
new file mode 100644
index 0000000..7d0a8a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u64 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
new file mode 100644
index 0000000..feb8a55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u8 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
new file mode 100644
index 0000000..366893d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
new file mode 100644
index 0000000..85dca2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p16 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
new file mode 100644
index 0000000..19fff80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p8 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
new file mode 100644
index 0000000..52bf8e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
new file mode 100644
index 0000000..4f8df90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s64 (void)
+{
+  int32x4_t out_int32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
new file mode 100644
index 0000000..a955553
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s8 (void)
+{
+  int32x4_t out_int32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
new file mode 100644
index 0000000..36f7a3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u16 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
new file mode 100644
index 0000000..b3200bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
new file mode 100644
index 0000000..009c931
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u64 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
new file mode 100644
index 0000000..59b13bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u8 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
new file mode 100644
index 0000000..27c6c5a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_f32 (void)
+{
+  int64x2_t out_int64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
new file mode 100644
index 0000000..ad92c9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p16 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
new file mode 100644
index 0000000..3850ba2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p8 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
new file mode 100644
index 0000000..b929cd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s16 (void)
+{
+  int64x2_t out_int64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
new file mode 100644
index 0000000..f095c80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
new file mode 100644
index 0000000..48cda7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s8 (void)
+{
+  int64x2_t out_int64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
new file mode 100644
index 0000000..175f18c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u16 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
new file mode 100644
index 0000000..4ad8745
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u32 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
new file mode 100644
index 0000000..5a52188
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
new file mode 100644
index 0000000..82d0757
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u8 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
new file mode 100644
index 0000000..851500f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_f32 (void)
+{
+  int8x16_t out_int8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
new file mode 100644
index 0000000..9f4b632
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p16 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
new file mode 100644
index 0000000..79d860c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p8 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
new file mode 100644
index 0000000..8434932
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s16 (void)
+{
+  int8x16_t out_int8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
new file mode 100644
index 0000000..c16a142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s32 (void)
+{
+  int8x16_t out_int8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
new file mode 100644
index 0000000..f383963
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s64 (void)
+{
+  int8x16_t out_int8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
new file mode 100644
index 0000000..19278ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u16 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
new file mode 100644
index 0000000..d5943f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u32 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
new file mode 100644
index 0000000..6e06637
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u64 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
new file mode 100644
index 0000000..1e95d19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
new file mode 100644
index 0000000..6068d0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_f32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
new file mode 100644
index 0000000..6ee38c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
new file mode 100644
index 0000000..feea098
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
new file mode 100644
index 0000000..59e49b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
new file mode 100644
index 0000000..38c2924
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
new file mode 100644
index 0000000..5fe8dda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
new file mode 100644
index 0000000..1afbd47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
new file mode 100644
index 0000000..59c5b97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
new file mode 100644
index 0000000..61d2b7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
new file mode 100644
index 0000000..243b991
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
new file mode 100644
index 0000000..c6d318f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
new file mode 100644
index 0000000..288654a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
new file mode 100644
index 0000000..cc8eec4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
new file mode 100644
index 0000000..9418c2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
new file mode 100644
index 0000000..69719d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
new file mode 100644
index 0000000..5b70d30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
new file mode 100644
index 0000000..90a2c7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
new file mode 100644
index 0000000..a331c9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
new file mode 100644
index 0000000..5c0e26c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
new file mode 100644
index 0000000..4b33783
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
new file mode 100644
index 0000000..17f89d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_f32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
new file mode 100644
index 0000000..50fbbde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
new file mode 100644
index 0000000..cc1d1e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
new file mode 100644
index 0000000..c17c800
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
new file mode 100644
index 0000000..dc8208b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
new file mode 100644
index 0000000..a4a08b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
new file mode 100644
index 0000000..357ceab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
new file mode 100644
index 0000000..62f9337
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
new file mode 100644
index 0000000..5d3a874
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
new file mode 100644
index 0000000..7618eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
new file mode 100644
index 0000000..4a21da5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_f32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
new file mode 100644
index 0000000..2977369
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
new file mode 100644
index 0000000..d8dd6de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
new file mode 100644
index 0000000..362a776
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
new file mode 100644
index 0000000..f864b1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
new file mode 100644
index 0000000..7cb682c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
new file mode 100644
index 0000000..8d803c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
new file mode 100644
index 0000000..14d94de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
new file mode 100644
index 0000000..0d8b469
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
new file mode 100644
index 0000000..8afdabf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
new file mode 100644
index 0000000..e05ef31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p16 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
new file mode 100644
index 0000000..6a80775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p8 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
new file mode 100644
index 0000000..d86ee65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s16 (void)
+{
+  float32x2_t out_float32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
new file mode 100644
index 0000000..10d230b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
new file mode 100644
index 0000000..c78cb78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s64 (void)
+{
+  float32x2_t out_float32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
new file mode 100644
index 0000000..bf130bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s8 (void)
+{
+  float32x2_t out_float32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
new file mode 100644
index 0000000..29f83cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u16 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
new file mode 100644
index 0000000..4da99af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
new file mode 100644
index 0000000..5bc91f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u64 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
new file mode 100644
index 0000000..655ed88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u8 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
new file mode 100644
index 0000000..78a6dc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_f32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
new file mode 100644
index 0000000..cd8c792
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
new file mode 100644
index 0000000..3638a18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
new file mode 100644
index 0000000..4d131a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
new file mode 100644
index 0000000..3d7e5d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
new file mode 100644
index 0000000..f72f660
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
new file mode 100644
index 0000000..f4b36ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
new file mode 100644
index 0000000..627eeef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
new file mode 100644
index 0000000..e7dbf83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
new file mode 100644
index 0000000..c00b726
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
new file mode 100644
index 0000000..c486793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_f32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
new file mode 100644
index 0000000..c8ff231
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
new file mode 100644
index 0000000..d179eae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
new file mode 100644
index 0000000..54deb03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
new file mode 100644
index 0000000..0788af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
new file mode 100644
index 0000000..e201471c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
new file mode 100644
index 0000000..34bc38d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
new file mode 100644
index 0000000..103963d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
new file mode 100644
index 0000000..4521146
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
new file mode 100644
index 0000000..52321f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
new file mode 100644
index 0000000..7cbe159
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_f32 (void)
+{
+  int16x4_t out_int16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
new file mode 100644
index 0000000..42533bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p16 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
new file mode 100644
index 0000000..6d2e15e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p8 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
new file mode 100644
index 0000000..019eb9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
new file mode 100644
index 0000000..56cdaed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s64 (void)
+{
+  int16x4_t out_int16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
new file mode 100644
index 0000000..f94745e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
new file mode 100644
index 0000000..4dc4f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
new file mode 100644
index 0000000..bf5442e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u32 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
new file mode 100644
index 0000000..42cc2c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u64 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
new file mode 100644
index 0000000..5f4baaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u8 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
new file mode 100644
index 0000000..5d646cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
new file mode 100644
index 0000000..7be758c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p16 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
new file mode 100644
index 0000000..3b3e34a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p8 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
new file mode 100644
index 0000000..deb72ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
new file mode 100644
index 0000000..9a1799d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
new file mode 100644
index 0000000..f8a6db9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s8 (void)
+{
+  int32x2_t out_int32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
new file mode 100644
index 0000000..3a1457d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u16 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
new file mode 100644
index 0000000..5c0cf56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
new file mode 100644
index 0000000..7ce200d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u64 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
new file mode 100644
index 0000000..9c1ebc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u8 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
new file mode 100644
index 0000000..b852607
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_f32 (void)
+{
+  int64x1_t out_int64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
new file mode 100644
index 0000000..aa49ee7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p16 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
new file mode 100644
index 0000000..0a9ff26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p8 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
new file mode 100644
index 0000000..beedbf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s16 (void)
+{
+  int64x1_t out_int64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
new file mode 100644
index 0000000..7d9060d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
new file mode 100644
index 0000000..9840119
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s8 (void)
+{
+  int64x1_t out_int64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
new file mode 100644
index 0000000..66313a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u16 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
new file mode 100644
index 0000000..a993b58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u32 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
new file mode 100644
index 0000000..67497a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
new file mode 100644
index 0000000..16ba5da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u8 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
new file mode 100644
index 0000000..b2f535b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_f32 (void)
+{
+  int8x8_t out_int8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
new file mode 100644
index 0000000..0ddbbbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p16 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
new file mode 100644
index 0000000..282fc93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p8 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
new file mode 100644
index 0000000..a23cdd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
new file mode 100644
index 0000000..e929929
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s32 (void)
+{
+  int8x8_t out_int8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
new file mode 100644
index 0000000..3288e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s64 (void)
+{
+  int8x8_t out_int8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
new file mode 100644
index 0000000..d24bd11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u16 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
new file mode 100644
index 0000000..7665a30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u32 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
new file mode 100644
index 0000000..e0fcde9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u64 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
new file mode 100644
index 0000000..a4da614
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
new file mode 100644
index 0000000..462d41b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_f32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
new file mode 100644
index 0000000..2d901d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
new file mode 100644
index 0000000..b49141b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
new file mode 100644
index 0000000..553deb1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
new file mode 100644
index 0000000..97ddbe3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
new file mode 100644
index 0000000..901288b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
new file mode 100644
index 0000000..10fec13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
new file mode 100644
index 0000000..3cc777d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
new file mode 100644
index 0000000..67ea82e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
new file mode 100644
index 0000000..b548558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
new file mode 100644
index 0000000..5a0bd36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
new file mode 100644
index 0000000..23e885c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
new file mode 100644
index 0000000..24df01f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
new file mode 100644
index 0000000..8e4baeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
new file mode 100644
index 0000000..5251786
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
new file mode 100644
index 0000000..0f0b489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
new file mode 100644
index 0000000..f2ca01d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
new file mode 100644
index 0000000..9ff8649
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
new file mode 100644
index 0000000..a7ab808
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
new file mode 100644
index 0000000..6dc3a30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
new file mode 100644
index 0000000..9d079aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_f32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
new file mode 100644
index 0000000..50a89b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
new file mode 100644
index 0000000..4d47d25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
new file mode 100644
index 0000000..f55f9ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
new file mode 100644
index 0000000..6ff562a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
new file mode 100644
index 0000000..1e705d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
new file mode 100644
index 0000000..d806467
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
new file mode 100644
index 0000000..97826c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
new file mode 100644
index 0000000..10a6b55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
new file mode 100644
index 0000000..d577d56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
new file mode 100644
index 0000000..e0e6a59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_f32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
new file mode 100644
index 0000000..d4e9852
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
new file mode 100644
index 0000000..ac17dd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
new file mode 100644
index 0000000..9182d4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
new file mode 100644
index 0000000..3eee2f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
new file mode 100644
index 0000000..46c65b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
new file mode 100644
index 0000000..c309adf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
new file mode 100644
index 0000000..e0c0bbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
new file mode 100644
index 0000000..4f61486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
new file mode 100644
index 0000000..a9df64a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
new file mode 100644
index 0000000..36af44e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
new file mode 100644
index 0000000..3a6b903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
new file mode 100644
index 0000000..859b1f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
new file mode 100644
index 0000000..8425192
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
new file mode 100644
index 0000000..c236a48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
new file mode 100644
index 0000000..9d640b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
new file mode 100644
index 0000000..1085713
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
new file mode 100644
index 0000000..4d28282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
new file mode 100644
index 0000000..d8af7a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
new file mode 100644
index 0000000..85fe2b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
new file mode 100644
index 0000000..8e26466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
new file mode 100644
index 0000000..4cd1024
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
new file mode 100644
index 0000000..41f4cf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
new file mode 100644
index 0000000..e1d7143
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
new file mode 100644
index 0000000..f013172
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
new file mode 100644
index 0000000..8d14e6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
new file mode 100644
index 0000000..abc5cde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
new file mode 100644
index 0000000..716a546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
new file mode 100644
index 0000000..a75d7da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
new file mode 100644
index 0000000..bbee8de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
new file mode 100644
index 0000000..f0f1628
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
new file mode 100644
index 0000000..0e24cc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
new file mode 100644
index 0000000..1c7c892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
new file mode 100644
index 0000000..e492a4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
new file mode 100644
index 0000000..1ed8330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
new file mode 100644
index 0000000..723a134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
new file mode 100644
index 0000000..4a6df77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
new file mode 100644
index 0000000..3a7c21e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64f32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
new file mode 100644
index 0000000..03c7e90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
new file mode 100644
index 0000000..91f1ea4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
new file mode 100644
index 0000000..c5e49d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
new file mode 100644
index 0000000..952365c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
new file mode 100644
index 0000000..8b4dc98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
new file mode 100644
index 0000000..6d92916
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
new file mode 100644
index 0000000..3759bb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
new file mode 100644
index 0000000..3328ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
new file mode 100644
index 0000000..a8ba1fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
new file mode 100644
index 0000000..609d789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
new file mode 100644
index 0000000..1a2b771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
new file mode 100644
index 0000000..6f4138d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
new file mode 100644
index 0000000..28d300e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
new file mode 100644
index 0000000..f02c99e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
new file mode 100644
index 0000000..c52ebb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
new file mode 100644
index 0000000..0ce8622
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
new file mode 100644
index 0000000..f8ef936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
new file mode 100644
index 0000000..823bbfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
new file mode 100644
index 0000000..003e169
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
new file mode 100644
index 0000000..16b1bc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
new file mode 100644
index 0000000..9c784cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
new file mode 100644
index 0000000..8ff74a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
new file mode 100644
index 0000000..9a22722
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
new file mode 100644
index 0000000..447f078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
new file mode 100644
index 0000000..c22690b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
new file mode 100644
index 0000000..c044b54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
new file mode 100644
index 0000000..49d0904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
new file mode 100644
index 0000000..c41b330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
new file mode 100644
index 0000000..76d1642
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
new file mode 100644
index 0000000..8f8c9e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
new file mode 100644
index 0000000..57cb6f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
new file mode 100644
index 0000000..45725c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
new file mode 100644
index 0000000..6f699c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
new file mode 100644
index 0000000..6639602
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
new file mode 100644
index 0000000..e22621a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
new file mode 100644
index 0000000..7bcfb67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
new file mode 100644
index 0000000..7c50d64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
new file mode 100644
index 0000000..e98bc6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
new file mode 100644
index 0000000..b4eeae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
new file mode 100644
index 0000000..aacac03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
new file mode 100644
index 0000000..01e3cfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
new file mode 100644
index 0000000..828bcdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
new file mode 100644
index 0000000..9e51c60d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
new file mode 100644
index 0000000..37fc479
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
new file mode 100644
index 0000000..eca26b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
new file mode 100644
index 0000000..8d20024
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
new file mode 100644
index 0000000..2d6a124
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
new file mode 100644
index 0000000..c74b1ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
new file mode 100644
index 0000000..1cd61e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
new file mode 100644
index 0000000..6601481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
new file mode 100644
index 0000000..845cb5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
new file mode 100644
index 0000000..1994c07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
new file mode 100644
index 0000000..caacaa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
new file mode 100644
index 0000000..553cd04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
new file mode 100644
index 0000000..b9081d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
new file mode 100644
index 0000000..ae26970
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
new file mode 100644
index 0000000..dbe74e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
new file mode 100644
index 0000000..271cc2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
new file mode 100644
index 0000000..fdec919
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
new file mode 100644
index 0000000..3c19612
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
new file mode 100644
index 0000000..fb68e32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
new file mode 100644
index 0000000..ebd7cef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
new file mode 100644
index 0000000..1b1fba4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
new file mode 100644
index 0000000..7bc3b10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
new file mode 100644
index 0000000..20bf363
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
new file mode 100644
index 0000000..a4a141c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc/testsuite/gcc.target/arm/neon/vshls16.c
new file mode 100644
index 0000000..80ab6f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc/testsuite/gcc.target/arm/neon/vshls32.c
new file mode 100644
index 0000000..f2cd655
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc/testsuite/gcc.target/arm/neon/vshls64.c
new file mode 100644
index 0000000..23c910f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc/testsuite/gcc.target/arm/neon/vshls8.c
new file mode 100644
index 0000000..798a23f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
new file mode 100644
index 0000000..6d7fbea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
new file mode 100644
index 0000000..be05c00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
new file mode 100644
index 0000000..687cae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
new file mode 100644
index 0000000..cb00705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
new file mode 100644
index 0000000..9bd0a80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
new file mode 100644
index 0000000..65c41a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
new file mode 100644
index 0000000..9ee9e48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
new file mode 100644
index 0000000..f8de705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
new file mode 100644
index 0000000..588ffb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
new file mode 100644
index 0000000..5044cbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
new file mode 100644
index 0000000..89d2c4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
new file mode 100644
index 0000000..80ee3f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
new file mode 100644
index 0000000..7576615
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
new file mode 100644
index 0000000..7b3c4fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
new file mode 100644
index 0000000..96ace08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
new file mode 100644
index 0000000..f8649d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
new file mode 100644
index 0000000..4ea2a53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
new file mode 100644
index 0000000..86ab08c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
new file mode 100644
index 0000000..331a997
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
new file mode 100644
index 0000000..6c94eaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
new file mode 100644
index 0000000..6ba1e4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
new file mode 100644
index 0000000..b84ddc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
new file mode 100644
index 0000000..6cb52f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
new file mode 100644
index 0000000..458698c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
new file mode 100644
index 0000000..b797205
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
new file mode 100644
index 0000000..f836841
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
new file mode 100644
index 0000000..d15239f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
new file mode 100644
index 0000000..9151aba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
new file mode 100644
index 0000000..82c1f6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
new file mode 100644
index 0000000..2496254
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
new file mode 100644
index 0000000..30139f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
new file mode 100644
index 0000000..abbe0c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
new file mode 100644
index 0000000..00e7cfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
new file mode 100644
index 0000000..155c705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
new file mode 100644
index 0000000..19570e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
new file mode 100644
index 0000000..85a77b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
new file mode 100644
index 0000000..d0395f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
new file mode 100644
index 0000000..22eef0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
new file mode 100644
index 0000000..12ba955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
new file mode 100644
index 0000000..7cb9804
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
new file mode 100644
index 0000000..822b05d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
new file mode 100644
index 0000000..dc01f50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
new file mode 100644
index 0000000..5bd4381
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
new file mode 100644
index 0000000..ba42363
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
new file mode 100644
index 0000000..84ef9f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
new file mode 100644
index 0000000..c62744d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
new file mode 100644
index 0000000..7e67969
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
new file mode 100644
index 0000000..db0869a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
new file mode 100644
index 0000000..f5ff91d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
new file mode 100644
index 0000000..909c73b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
new file mode 100644
index 0000000..f437b33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
new file mode 100644
index 0000000..41e1b54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
new file mode 100644
index 0000000..b70347f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
new file mode 100644
index 0000000..62afb61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
new file mode 100644
index 0000000..6a19cd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
new file mode 100644
index 0000000..3ed528c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
new file mode 100644
index 0000000..9a5ce96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
new file mode 100644
index 0000000..f1de791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
new file mode 100644
index 0000000..0143526
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
new file mode 100644
index 0000000..d7e3bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
new file mode 100644
index 0000000..bf9e1df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
new file mode 100644
index 0000000..bc05cc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
new file mode 100644
index 0000000..efa39e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
new file mode 100644
index 0000000..376e8d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
new file mode 100644
index 0000000..f69c52b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
new file mode 100644
index 0000000..6108d36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
new file mode 100644
index 0000000..d78710f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
new file mode 100644
index 0000000..ba4bd19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
new file mode 100644
index 0000000..c15a1f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
new file mode 100644
index 0000000..634be97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
new file mode 100644
index 0000000..85812e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
new file mode 100644
index 0000000..d83121f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
new file mode 100644
index 0000000..7080997
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
new file mode 100644
index 0000000..abb742f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
new file mode 100644
index 0000000..5eaee78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
new file mode 100644
index 0000000..c813765
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
new file mode 100644
index 0000000..552c5db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
new file mode 100644
index 0000000..9bec2ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
new file mode 100644
index 0000000..001bc33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
new file mode 100644
index 0000000..8bb73bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
new file mode 100644
index 0000000..bad5816
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
new file mode 100644
index 0000000..c2cc93dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
new file mode 100644
index 0000000..e1de667
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
new file mode 100644
index 0000000..f2a4f59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
new file mode 100644
index 0000000..f4a56b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
new file mode 100644
index 0000000..0a7de3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
new file mode 100644
index 0000000..5211c9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
new file mode 100644
index 0000000..ab1bda9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
new file mode 100644
index 0000000..215c5af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
new file mode 100644
index 0000000..4e88d26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
new file mode 100644
index 0000000..2d416c0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
new file mode 100644
index 0000000..46fe4c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
new file mode 100644
index 0000000..9536e37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
new file mode 100644
index 0000000..e8bab5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
new file mode 100644
index 0000000..b836695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
new file mode 100644
index 0000000..bdbf4b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
new file mode 100644
index 0000000..c3c04aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
new file mode 100644
index 0000000..54fc0bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
new file mode 100644
index 0000000..696b4ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
new file mode 100644
index 0000000..6de3700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
new file mode 100644
index 0000000..b0667fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
new file mode 100644
index 0000000..88456cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
new file mode 100644
index 0000000..8a390f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
new file mode 100644
index 0000000..0e815e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
new file mode 100644
index 0000000..03fe37d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
new file mode 100644
index 0000000..793b8a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
new file mode 100644
index 0000000..50de02d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
new file mode 100644
index 0000000..e8d31d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
new file mode 100644
index 0000000..73bbe63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
new file mode 100644
index 0000000..61b08a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
new file mode 100644
index 0000000..263113b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
new file mode 100644
index 0000000..8fe92a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
new file mode 100644
index 0000000..65785ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
new file mode 100644
index 0000000..6f54cc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
new file mode 100644
index 0000000..2e96ddf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
new file mode 100644
index 0000000..fc6829b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
new file mode 100644
index 0000000..138b7f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
new file mode 100644
index 0000000..ae57e3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
new file mode 100644
index 0000000..7c29312
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
new file mode 100644
index 0000000..968447a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
new file mode 100644
index 0000000..2e69436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
new file mode 100644
index 0000000..ab8daca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
new file mode 100644
index 0000000..77265c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
new file mode 100644
index 0000000..ef92684
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
new file mode 100644
index 0000000..6cc6d2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
new file mode 100644
index 0000000..92a37cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
new file mode 100644
index 0000000..4d36a80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
new file mode 100644
index 0000000..c3247d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
new file mode 100644
index 0000000..60c0c14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
new file mode 100644
index 0000000..82c3094
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
new file mode 100644
index 0000000..f966f8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
new file mode 100644
index 0000000..9360092
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
new file mode 100644
index 0000000..5109dc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
new file mode 100644
index 0000000..dba266d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
new file mode 100644
index 0000000..1de0052
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x2_t arg1_poly8x16x2_t;
+
+  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
new file mode 100644
index 0000000..83fe852
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
new file mode 100644
index 0000000..ea8411f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
new file mode 100644
index 0000000..1eb70b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x2_t arg1_int8x16x2_t;
+
+  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
new file mode 100644
index 0000000..61dfaee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
new file mode 100644
index 0000000..ec85560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
new file mode 100644
index 0000000..c3e5c5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x2_t arg1_uint8x16x2_t;
+
+  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
new file mode 100644
index 0000000..4dc5258
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
new file mode 100644
index 0000000..dedaec7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
new file mode 100644
index 0000000..ff88aeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
new file mode 100644
index 0000000..80aedba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
new file mode 100644
index 0000000..150686d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
new file mode 100644
index 0000000..a71f186
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
new file mode 100644
index 0000000..303b8ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
new file mode 100644
index 0000000..e1402fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
new file mode 100644
index 0000000..37f320b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
new file mode 100644
index 0000000..4b1d03d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
new file mode 100644
index 0000000..9e788b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
new file mode 100644
index 0000000..d40ca69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
new file mode 100644
index 0000000..56cdbf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
new file mode 100644
index 0000000..9519eec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
new file mode 100644
index 0000000..e4fda8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x2_t arg1_int64x1x2_t;
+
+  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
new file mode 100644
index 0000000..9553e4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
new file mode 100644
index 0000000..c0af478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
new file mode 100644
index 0000000..dbde9a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
new file mode 100644
index 0000000..2487ff2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x2_t arg1_uint64x1x2_t;
+
+  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
new file mode 100644
index 0000000..e35a3cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
new file mode 100644
index 0000000..c8409af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
new file mode 100644
index 0000000..1c058b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
new file mode 100644
index 0000000..a6c0c1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
new file mode 100644
index 0000000..982d4de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
new file mode 100644
index 0000000..c44b1a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
new file mode 100644
index 0000000..7ddf888
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
new file mode 100644
index 0000000..c8d5d22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
new file mode 100644
index 0000000..6b416bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
new file mode 100644
index 0000000..7b034fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x3_t arg1_poly8x16x3_t;
+
+  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
new file mode 100644
index 0000000..c191ea0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
new file mode 100644
index 0000000..5fad79b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
new file mode 100644
index 0000000..ba5807e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x3_t arg1_int8x16x3_t;
+
+  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
new file mode 100644
index 0000000..7d23e10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
new file mode 100644
index 0000000..c6233c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
new file mode 100644
index 0000000..a72a4a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x3_t arg1_uint8x16x3_t;
+
+  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
new file mode 100644
index 0000000..f4e4a48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
new file mode 100644
index 0000000..af61dcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
new file mode 100644
index 0000000..b5d21c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
new file mode 100644
index 0000000..0f5d9d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
new file mode 100644
index 0000000..9bd76f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
new file mode 100644
index 0000000..b7f5996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
new file mode 100644
index 0000000..d008562
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
new file mode 100644
index 0000000..2e4bf4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
new file mode 100644
index 0000000..c001b09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
new file mode 100644
index 0000000..6cd8518
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
new file mode 100644
index 0000000..d3deb3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
new file mode 100644
index 0000000..41f9608
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
new file mode 100644
index 0000000..73cb693
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
new file mode 100644
index 0000000..46feb60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
new file mode 100644
index 0000000..93834d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x3_t arg1_int64x1x3_t;
+
+  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
new file mode 100644
index 0000000..f093584
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
new file mode 100644
index 0000000..dc634f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
new file mode 100644
index 0000000..a7eeef4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
new file mode 100644
index 0000000..4cd8440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x3_t arg1_uint64x1x3_t;
+
+  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
new file mode 100644
index 0000000..83c6155
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
new file mode 100644
index 0000000..937168e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
new file mode 100644
index 0000000..549360c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
new file mode 100644
index 0000000..b9b25fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
new file mode 100644
index 0000000..cab45ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
new file mode 100644
index 0000000..61aba31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
new file mode 100644
index 0000000..98144c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
new file mode 100644
index 0000000..ad51afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
new file mode 100644
index 0000000..1ab6337
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
new file mode 100644
index 0000000..3e32382
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x4_t arg1_poly8x16x4_t;
+
+  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
new file mode 100644
index 0000000..8581c41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
new file mode 100644
index 0000000..8a66e96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
new file mode 100644
index 0000000..14e8ab8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x4_t arg1_int8x16x4_t;
+
+  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
new file mode 100644
index 0000000..5f14fa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
new file mode 100644
index 0000000..e427446
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
new file mode 100644
index 0000000..b67bb19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x4_t arg1_uint8x16x4_t;
+
+  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
new file mode 100644
index 0000000..8d0eab5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
new file mode 100644
index 0000000..7dbddf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
new file mode 100644
index 0000000..1791964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
new file mode 100644
index 0000000..46a4c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
new file mode 100644
index 0000000..1a9491c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
new file mode 100644
index 0000000..15cbab1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
new file mode 100644
index 0000000..96a0182
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
new file mode 100644
index 0000000..c8b1922
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
new file mode 100644
index 0000000..0dbcd54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
new file mode 100644
index 0000000..9e37af2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
new file mode 100644
index 0000000..f07d435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
new file mode 100644
index 0000000..ddee228
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
new file mode 100644
index 0000000..8ca8060
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
new file mode 100644
index 0000000..9619e4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
new file mode 100644
index 0000000..0b470ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x4_t arg1_int64x1x4_t;
+
+  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
new file mode 100644
index 0000000..796c446
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
new file mode 100644
index 0000000..3ce82b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
new file mode 100644
index 0000000..36df649
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
new file mode 100644
index 0000000..3d11dd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x4_t arg1_uint64x1x4_t;
+
+  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
new file mode 100644
index 0000000..4d4dde1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
new file mode 100644
index 0000000..bacf304
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
new file mode 100644
index 0000000..01b4f6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
new file mode 100644
index 0000000..1de3a94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
new file mode 100644
index 0000000..1ac90a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
new file mode 100644
index 0000000..e3b819b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
new file mode 100644
index 0000000..46ad52b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
new file mode 100644
index 0000000..391f54c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
new file mode 100644
index 0000000..f542d37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
new file mode 100644
index 0000000..1f8ec0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
new file mode 100644
index 0000000..ee29262
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
new file mode 100644
index 0000000..034e87a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
new file mode 100644
index 0000000..5c5d0bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
new file mode 100644
index 0000000..2e7e5ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
new file mode 100644
index 0000000..91f6aa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
new file mode 100644
index 0000000..36ce23e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
new file mode 100644
index 0000000..bde5a7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
new file mode 100644
index 0000000..f346d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
new file mode 100644
index 0000000..db618901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
new file mode 100644
index 0000000..e3cad6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
new file mode 100644
index 0000000..cb30129
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
new file mode 100644
index 0000000..e9541f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
new file mode 100644
index 0000000..51f68dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
new file mode 100644
index 0000000..1b97aef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
new file mode 100644
index 0000000..11e1a37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
new file mode 100644
index 0000000..85074fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
new file mode 100644
index 0000000..4cfe5db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
new file mode 100644
index 0000000..d1039ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
new file mode 100644
index 0000000..eca7e86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
new file mode 100644
index 0000000..e6307c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
new file mode 100644
index 0000000..02b945c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
new file mode 100644
index 0000000..a821ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
new file mode 100644
index 0000000..4e1e7dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
new file mode 100644
index 0000000..2230508
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
new file mode 100644
index 0000000..e35073b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
new file mode 100644
index 0000000..e4270aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
new file mode 100644
index 0000000..5d8aa55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
new file mode 100644
index 0000000..177db25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
new file mode 100644
index 0000000..1e77e30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
new file mode 100644
index 0000000..8719c28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
new file mode 100644
index 0000000..07bdc05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x2_t arg0_poly8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
new file mode 100644
index 0000000..04a824d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x2_t arg0_int8x8x2_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
new file mode 100644
index 0000000..ce29a23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x2_t arg0_uint8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
new file mode 100644
index 0000000..dce7bbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x3_t arg0_poly8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
new file mode 100644
index 0000000..1b62f6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x3_t arg0_int8x8x3_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
new file mode 100644
index 0000000..9837e53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x3_t arg0_uint8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
new file mode 100644
index 0000000..c60e2dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x4_t arg0_poly8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
new file mode 100644
index 0000000..c89d2b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x4_t arg0_int8x8x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
new file mode 100644
index 0000000..1e98a31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x4_t arg0_uint8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
new file mode 100644
index 0000000..136d80e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
new file mode 100644
index 0000000..23e5983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
new file mode 100644
index 0000000..4632063
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
new file mode 100644
index 0000000..2b46e7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
new file mode 100644
index 0000000..6efb84f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
new file mode 100644
index 0000000..a745689
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
new file mode 100644
index 0000000..a8f9a29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
new file mode 100644
index 0000000..9de0184
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
new file mode 100644
index 0000000..45e7e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
new file mode 100644
index 0000000..a283be7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
new file mode 100644
index 0000000..f64198c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
new file mode 100644
index 0000000..de5ebd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
new file mode 100644
index 0000000..c011dc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
new file mode 100644
index 0000000..3f86f8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
new file mode 100644
index 0000000..2406d88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
new file mode 100644
index 0000000..971977a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
new file mode 100644
index 0000000..b895586
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
new file mode 100644
index 0000000..c7a62b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
new file mode 100644
index 0000000..e36b18d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
new file mode 100644
index 0000000..dee79ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
new file mode 100644
index 0000000..7fbffd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
new file mode 100644
index 0000000..c31e250
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
new file mode 100644
index 0000000..f2d0357
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
new file mode 100644
index 0000000..97eb848
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
new file mode 100644
index 0000000..98ddc52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
new file mode 100644
index 0000000..ae02e6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
new file mode 100644
index 0000000..6d45572
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
new file mode 100644
index 0000000..4f7a6da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
new file mode 100644
index 0000000..b9a9dbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
new file mode 100644
index 0000000..4de2496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
new file mode 100644
index 0000000..38f8a4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
new file mode 100644
index 0000000..607a01e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
new file mode 100644
index 0000000..b2b3def
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
new file mode 100644
index 0000000..d5faf9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
new file mode 100644
index 0000000..8dfa203
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
new file mode 100644
index 0000000..024e578
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
new file mode 100644
index 0000000..0d7f3b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
new file mode 100644
index 0000000..93327b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
new file mode 100644
index 0000000..30b7884
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
new file mode 100644
index 0000000..f5dafb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
new file mode 100644
index 0000000..f4c4162
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
new file mode 100644
index 0000000..6f8005c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
new file mode 100644
index 0000000..b98e12c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
new file mode 100644
index 0000000..0c7f380
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
new file mode 100644
index 0000000..2933956
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
new file mode 100644
index 0000000..51a90d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
new file mode 100644
index 0000000..f976565
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
new file mode 100644
index 0000000..aeb2967
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
new file mode 100644
index 0000000..3bf1ad9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
new file mode 100644
index 0000000..194b596
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
new file mode 100644
index 0000000..6312ca7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
new file mode 100644
index 0000000..f7d854c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
new file mode 100644
index 0000000..eef40e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
new file mode 100644
index 0000000..056795e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
new file mode 100644
index 0000000..d198675
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
new file mode 100644
index 0000000..292a228
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
new file mode 100644
index 0000000..3d65903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
new file mode 100644
index 0000000..68767dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
new file mode 100644
index 0000000..ef9704c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
new file mode 100644
index 0000000..f6d4636
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
new file mode 100644
index 0000000..33b75c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
new file mode 100644
index 0000000..99fec5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
new file mode 100644
index 0000000..f1d0393
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
new file mode 100644
index 0000000..d378c51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
new file mode 100644
index 0000000..ce557b78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
new file mode 100644
index 0000000..b629a40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
new file mode 100644
index 0000000..09c0ef6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
new file mode 100644
index 0000000..6bc9461
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
new file mode 100644
index 0000000..7439290
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
new file mode 100644
index 0000000..d499070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
new file mode 100644
index 0000000..35d0ef6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
new file mode 100644
index 0000000..e1f7ff1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
new file mode 100644
index 0000000..e8a62b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
new file mode 100644
index 0000000..553b691
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc/testsuite/gcc.target/arm/neon/vzips16.c
new file mode 100644
index 0000000..0693ee7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips16.c
@@ -0,0 +1,20 @@
+/* Test the `vzips16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc/testsuite/gcc.target/arm/neon/vzips32.c
new file mode 100644
index 0000000..29990f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips32.c
@@ -0,0 +1,20 @@
+/* Test the `vzips32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc/testsuite/gcc.target/arm/neon/vzips8.c
new file mode 100644
index 0000000..9546ad8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips8.c
@@ -0,0 +1,20 @@
+/* Test the `vzips8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
new file mode 100644
index 0000000..ebcb9f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
new file mode 100644
index 0000000..6ba6c32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
new file mode 100644
index 0000000..94a280c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp
index f7877c9..db50df3 100644
--- a/gcc/testsuite/lib/gcc-dg.exp
+++ b/gcc/testsuite/lib/gcc-dg.exp
@@ -427,8 +427,8 @@ proc cleanup-dump { suffix } {
 
 # Remove files kept by --save-temps for the current test.
 #
-# Currently this is only .i files, but more can be added if there are
-# tests generating them.
+# Currently this is only .i, .ii and .s files, but more can be added
+# if there are tests generating them.
 proc cleanup-saved-temps { } {
     global additional_sources
 
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index ea3ecc4..0a0405e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1462,6 +1462,74 @@ proc check_effective_target_arm_vfp_ok { } {
     }
 }
 
+# Return 1 if this is an ARM target supporting -mfpu=neon
+# -mfloat-abi=softfp.  Some multilibs may be incompatible with these
+# options.
+
+proc check_effective_target_arm_neon_ok { } {
+    if { [check_effective_target_arm32] } {
+        return [check_no_compiler_messages arm_neon_ok object {
+            int dummy;
+        } "-mfpu=neon -mfloat-abi=softfp"]
+    } else {
+        return 0
+    }
+}
+
+# Return 1 if the target supports executing NEON instructions, 0
+# otherwise.  Cache the result.
+
+proc check_effective_target_arm_neon_hw { } {
+    global arm_neon_hw_available_saved
+    global tool
+
+    if [info exists arm_neon_hw_available_saved] {
+        verbose "check_arm_neon_hw_available  returning saved $arm_neon_hw_avail
+able_saved" 2
+    } else {
+        set arm_neon_hw_available_saved 0
+
+        # Set up, compile, and execute a test program containing NEON
+        # instructions.  Include the current process ID in the file
+        # names to prevent conflicts with invocations for multiple
+        # testsuites.
+        set src neon[pid].c
+        set exe neon[pid].x
+
+        set f [open $src "w"]
+        puts $f "int main() {"
+        puts $f "  long long a = 0, b = 1;"
+        puts $f "  asm (\"vorr %P0, %P1, %P2\""
+        puts $f "       : \"=w\" (a)"
+        puts $f "       : \"0\" (a), \"w\" (b));"
+        puts $f "  return (a != 1);"
+        puts $f "}"
+        close $f
+
+        set opts "additional_flags=-mfpu=neon additional_flags=-mfloat-abi=softfp"
+
+        verbose "check_arm_neon_hw_available  compiling testfile $src" 2
+        set lines [${tool}_target_compile $src $exe executable "$opts"]
+        file delete $src
+
+        if [string match "" $lines] then {
+            # No error message, compilation succeeded.
+            set result [${tool}_load "./$exe" "" ""]
+            set status [lindex $result 0]
+            remote_file build delete $exe
+            verbose "check_arm_neon_hw_available testfile status is <$status>" 2
+
+            if { $status == "pass" } then {
+                set arm_neon_hw_available_saved 1
+            }
+        } else {
+            verbose "check_arm_neon_hw_available testfile compilation failed" 2
+        }
+    }
+
+    return $arm_neon_hw_available_saved
+}
+
 # Return 1 if this is a PowerPC target with floating-point registers.
 
 proc check_effective_target_powerpc_fprs { } {