i386: Add v<any_shift:insn>v4qi3 expander

Also, move v<any_shift:insn>v8qi3 expander to a better place and enable
it with TARGET_MMX_WITH_SSE.  Remove handling of V8QImode from
ix86_expand_vecop_qihi2 since all partial QI->HI vector modes expand
via ix86_expand_vecop_qihi_partial.

gcc/ChangeLog:

	* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
	Remove handling of V8QImode.
	* config/i386/mmx.md (v<insn>v8qi3): Move from sse.md.
	Call ix86_expand_vecop_qihi_partial.  Enable for TARGET_MMX_WITH_SSE.
	(v<insn>v4qi3): Ditto.
	* config/i386/sse.md (v<insn>v8qi3): Remove.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/vect-shiftv4qi.c (dg-options):
	Remove -ftree-vectorize.
	* gcc.target/i386/vect-shiftv8qi.c (dg-options): Ditto.
	* gcc.target/i386/vect-vshiftv4qi.c: New test.
	* gcc.target/i386/vect-vshiftv8qi.c: New test.

4 files changed, 58 insertions, 2 deletions

diff --git a/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c b/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c
index c06dfb8..c6a6390 100644
--- a/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c
+++ b/gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+/* { dg-options "-O2 -msse2" } */
 
 #define N 4
 
diff --git a/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c b/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c
index f5e8925..244b0db 100644
--- a/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c
+++ b/gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+/* { dg-options "-O2 -msse2" } */
 
 #define N 8
 
diff --git a/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c b/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c
new file mode 100644
index 0000000..c74cc99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl" } */
+
+#define N 4
+
+typedef unsigned char __vu __attribute__ ((__vector_size__ (N)));
+typedef signed char __vi __attribute__ ((__vector_size__ (N)));
+
+__vu sllv (__vu a, __vu b)
+{
+  return a << b;
+}
+
+/* { dg-final { scan-assembler-times "vpsllvw" 1 } } */
+
+__vu srlv (__vu a, __vu b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler-times "vpsrlvw" 1 } } */
+
+__vi srav (__vi a, __vi b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler-times "vpsravw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c b/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c
new file mode 100644
index 0000000..1d838af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl" } */
+
+#define N 8
+
+typedef unsigned char __vu __attribute__ ((__vector_size__ (N)));
+typedef signed char __vi __attribute__ ((__vector_size__ (N)));
+
+__vu vsll (__vu a, __vu b)
+{
+  return a << b;
+}
+
+/* { dg-final { scan-assembler-times "vpsllvw" 1 } } */
+
+__vu vsrl (__vu a, __vu b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler-times "vpsrlvw" 1 } } */
+
+__vi vsra (__vi a, __vi b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler-times "vpsravw" 1 } } */