tree-ssa-math-opts: Small uaddc/usubc pattern matching improvement [PR79173]

In the following testcase we fail to pattern recognize the least significant
.UADDC call.  The reason is that arg3 in that case is
  _3 = .ADD_OVERFLOW (...);
  _2 = __imag__ _3;
  _1 = _2 != 0;
  arg3 = (unsigned long) _1;
and while before the changes arg3 has a single use in some .ADD_OVERFLOW
later on, we add a .UADDC call next to it (and gsi_remove/gsi_replace only
what is strictly necessary and leave quite a few dead stmts around which
next DCE cleans up) and so it all of sudden isn't used just once, but twice
(.ADD_OVERFLOW and .UADDC) and so uaddc_cast fails.  While we could tweak
uaddc_cast and not require has_single_use in these uses, there is also
no vrp that would figure out that because __imag__ _3 is in [0, 1] range,
it can just use arg3 = __imag__ _3; and drop the comparison and cast.

We already search if either arg2 or arg3 is ultimately set from __imag__
of .{{ADD,SUB}_OVERFLOW,U{ADD,SUB}C} call, so the following patch just
remembers the lhs of __imag__ from that case and uses it later.

2023-06-20  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/79173
	* tree-ssa-math-opts.cc (match_uaddc_usubc): Remember lhs of
	IMAGPART_EXPR of arg2/arg3 and use that as arg3 if it has the right
	type.

	* g++.target/i386/pr79173-1.C: New test.

1 files changed, 33 insertions, 0 deletions

diff --git a/gcc/testsuite/g++.target/i386/pr79173-1.C b/gcc/testsuite/g++.target/i386/pr79173-1.C
new file mode 100644
index 0000000..e6fc7cb
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr79173-1.C
@@ -0,0 +1,33 @@
+// PR middle-end/79173
+// { dg-do compile { target c++11 } }
+// { dg-options "-O2 -fno-stack-protector -masm=att" }
+// { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+
+template <typename T>
+inline constexpr T
+uaddc (T x, T y, T carry_in, T &carry_out) noexcept
+{
+  [[gnu::assume (carry_in <= 1)]];
+  x += y;
+  carry_out = x < y;
+  x += carry_in;
+  carry_out += x < carry_in;
+  return x;
+}
+
+void
+foo (unsigned long *p, unsigned long *q)
+{
+  unsigned long c;
+  p[0] = uaddc (p[0], q[0], 0UL, c);
+  p[1] = uaddc (p[1], q[1], c, c);
+  p[2] = uaddc (p[2], q[2], c, c);
+  p[3] = uaddc (p[3], q[3], c, c);
+}