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| author | Ian Lance Taylor <iant@golang.org> | 2021-09-17 08:46:39 -0700 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2021-09-17 08:46:39 -0700 |
| commit | a0791d0ed4f147ef347e83f4aedc7ad03f1a2008 (patch) | |
| tree | 7b3526910798e4cff7a7200d684383046bac6225 /gcc/testsuite | |
| parent | e252b51ccde010cbd2a146485d8045103cd99533 (diff) | |
| parent | 89be17a1b231ade643f28fbe616d53377e069da8 (diff) | |
| download | gcc-a0791d0ed4f147ef347e83f4aedc7ad03f1a2008.zip gcc-a0791d0ed4f147ef347e83f4aedc7ad03f1a2008.tar.gz gcc-a0791d0ed4f147ef347e83f4aedc7ad03f1a2008.tar.bz2 | |
Merge from trunk revision 89be17a1b231ade643f28fbe616d53377e069da8.
Diffstat (limited to 'gcc/testsuite')
252 files changed, 9452 insertions, 146 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 137382c..1c8d4ba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,421 @@ +2021-09-16 Patrick Palka <ppalka@redhat.com> + + PR c++/98486 + * g++.dg/cpp2a/concepts-var-templ1.C: New test. + * g++.dg/cpp2a/concepts-var-templ1a.C: New test. + * g++.dg/cpp2a/concepts-var-templ1b.C: New test. + +2021-09-16 Harald Anlauf <anlauf@gmx.de> + + PR fortran/102287 + * gfortran.dg/intent_out_14.f90: New test. + +2021-09-16 Richard Biener <rguenther@suse.de> + + PR middle-end/102360 + * g++.dg/pr102360.C: New testcase. + +2021-09-16 Richard Earnshaw <rearnsha@arm.com> + + * g++.dg/eh/arm-vfp-unwind.C: Support single-precision. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + PR middle-end/102080 + * gcc.target/i386/pr102080.c: New test. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c: New test. + * gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtw2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtw2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c: Ditto. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-helper.h (V512): Add QI + components. + * gcc.target/i386/avx512fp16-vcvtph2dq-1a.c: New test. + * gcc.target/i386/avx512fp16-vcvtph2dq-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2qq-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2qq-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2udq-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2udq-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2uw-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2uw-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2w-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vcvtph2w-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c: Ditto. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-16 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-vmovsh-1a.c: New test. + * gcc.target/i386/avx512fp16-vmovsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-2a.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-2b.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-3a.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-3b.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-4a.c: Ditto. + * gcc.target/i386/avx512fp16-vmovw-4b.c: Ditto. + +2021-09-15 Patrick Palka <ppalka@redhat.com> + + PR c++/101904 + * g++.dg/ext/conv2.C: New test. + * g++.dg/template/conv17.C: Extend test. + +2021-09-15 Jakub Jelinek <jakub@redhat.com> + + PR c++/88578 + PR c++/102295 + * g++.dg/ext/flexary39.C: New test. + * g++.dg/ext/flexary40.C: New test. + +2021-09-15 Patrick Palka <ppalka@redhat.com> + + PR c++/102050 + * g++.dg/cpp0x/initlist125.C: New test. + * g++.dg/cpp0x/initlist126.C: New test. + +2021-09-15 Alexandre Oliva <oliva@adacore.com> + + * gnat.dg/zcur_attr.adb, gnat.dg/zcur_attr.ads: New. + +2021-09-15 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/pr102327-1.c: New test. + * gcc.target/i386/pr102327-2.c: New test. + * gcc.target/i386/avx512fp16-1c.c: Adjust testcase. + +2021-09-15 Hongyu Wang <hongyu.wang@intel.com> + + * gcc.target/i386/avx-1.c: Adjust builtin macros. + * gcc.target/i386/sse-13.c: Likewise. + * gcc.target/i386/sse-23.c: Likewise. + +2021-09-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/102318 + * gcc.dg/vect/pr102318.c: New testcase. + +2021-09-15 Hongtao Liu <hongtao.liu@intel.com> + Peter Cordes <peter@cordes.ca> + + PR target/91103 + * gcc.target/i386/pr91103-1.c: Add extract tests. + * gcc.target/i386/pr91103-2.c: Ditto. + +2021-09-15 Thomas Schwinge <thomas@codesourcery.com> + + * gfortran.dg/goacc/unexpected-end.f90: Add OpenACC 'host_data' + testing. + +2021-09-15 Jason Merrill <jason@redhat.com> + + PR c++/48396 + * g++.dg/rtti/undeclared1.C: New test. + +2021-09-14 Harald Anlauf <anlauf@gmx.de> + + PR fortran/102311 + * gfortran.dg/entry_25.f90: New test. + +2021-09-14 Peter Bergner <bergner@linux.ibm.com> + + * gcc.target/powerpc/mma-builtin-6.c: Add second call to xxsetacc + built-in. Update instruction counts. + +2021-09-14 Patrick Palka <ppalka@redhat.com> + + PR c++/102163 + * g++.dg/cpp0x/constexpr-empty17.C: New test. + +2021-09-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/102295 + * g++.target/i386/pr102295.C: New test. + +2021-09-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/102305 + * g++.dg/cpp0x/pr102305.C: New test. + +2021-09-14 Tobias Burnus <tobias@codesourcery.com> + + PR fortran/102313 + * gfortran.dg/goacc/unexpected-end.f90: New test. + * gfortran.dg/gomp/unexpected-end.f90: New test. + +2021-09-14 Martin Liska <mliska@suse.cz> + + * g++.dg/gcov/gcov.py: Fix failing pytests as gcov.json.gz + filename was changed in b777f228b481ae881a7fbb09de367a053740932c. + +2021-09-14 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/enum_rep2.adb: New test. + +2021-09-14 Jakub Jelinek <jakub@redhat.com> + + * c-c++-common/gomp/atomic-29.c: Add -march=pentium + dg-additional-options for ia32. Use sync_long_long effective target + instead of sync_int_long. + * lib/target-supports.exp (check_effective_target_sync_long_long): Fix + a syntax error. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-helper.h (V512): + Add xmm component. + * gcc.target/i386/avx512fp16-vfpclassph-1a.c: New test. + * gcc.target/i386/avx512fp16-vfpclassph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vfpclasssh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vfpclasssh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vgetexpph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vgetexpph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vgetexpsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vgetexpsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vgetmantph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vgetmantph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vgetmantsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vgetmantsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vfpclassph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vfpclassph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vgetexpph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vgetexpph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vgetmantph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vgetmantph-1b.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-helper.h (_ROUND_CUR): New macro. + * gcc.target/i386/avx512fp16-vreduceph-1a.c: New test. + * gcc.target/i386/avx512fp16-vreduceph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vreducesh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vreducesh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vrndscaleph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vrndscaleph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vrndscalesh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vrndscalesh-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vreduceph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vreduceph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-vrcpph-1a.c: New test. + * gcc.target/i386/avx512fp16-vrcpph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vrcpsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vrcpsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vscalefph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vscalefph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vscalefsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vscalefsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrcpph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrcpph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vscalefph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vscalefph-1b.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512fp16-vrsqrtph-1a.c: New test. + * gcc.target/i386/avx512fp16-vrsqrtph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vrsqrtsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vrsqrtsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vsqrtph-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vsqrtph-1b.c: Ditto. + * gcc.target/i386/avx512fp16-vsqrtsh-1a.c: Ditto. + * gcc.target/i386/avx512fp16-vsqrtsh-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c: Ditto. + * gcc.target/i386/avx512fp16vl-vsqrtph-1a.c: Ditto. + * gcc.target/i386/avx512fp16vl-vsqrtph-1b.c: Ditto. + +2021-09-14 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx-1.c: Add test for new builtins. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * gcc.target/i386/sse-14.c: Add test for new intrinsics. + * gcc.target/i386/sse-22.c: Ditto. + +2021-09-13 Harald Anlauf <anlauf@gmx.de> + + PR fortran/82314 + * gfortran.dg/pr82314.f90: New test. + +2021-09-13 Harald Anlauf <anlauf@gmx.de> + + PR fortran/85130 + * gfortran.dg/substr_6.f90: Revert commit r8-7574, adding again + test that was erroneously considered as illegal. + +2021-09-13 Jason Merrill <jason@redhat.com> + + * g++.dg/warn/Winterference.H: New file. + * g++.dg/warn/Winterference.C: New test. + * g++.target/aarch64/interference.C: New test. + * g++.target/arm/interference.C: New test. + * g++.target/i386/interference.C: New test. + * g++.dg/warn/Winterference-2.C: New file. + +2021-09-13 Martin Liska <mliska@suse.cz> + H.J. Lu <hjl.tools@gmail.com> + + PR target/101696 + * g++.target/i386/mv30.C: New test. + * gcc.target/i386/mvc16.c: New test. + * gcc.target/i386/builtin_target.c (CHECK___builtin_cpu_supports): + New. + +2021-09-13 Andrew Pinski <apinski@marvell.com> + + PR target/95969 + * gcc.target/aarch64/lane-bound-1.c: New test. + * gcc.target/aarch64/lane-bound-2.c: New test. + +2021-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/102252 + * g++.target/aarch64/sve/pr102252.C: New test. + +2021-09-13 Aldy Hernandez <aldyh@redhat.com> + + * gcc.dg/tree-ssa/pr21417.c: Adjust for FSM removal. + * gcc.dg/tree-ssa/pr66752-3.c: Same. + * gcc.dg/tree-ssa/pr68198.c: Same. + * gcc.dg/tree-ssa/pr69196-1.c: Same. + * gcc.dg/tree-ssa/pr70232.c: Same. + * gcc.dg/tree-ssa/pr77445.c: Same. + * gcc.dg/tree-ssa/ranger-threader-4.c: Same. + * gcc.dg/tree-ssa/ssa-dom-thread-18.c: Same. + * gcc.dg/tree-ssa/ssa-dom-thread-6.c: Same. + * gcc.dg/tree-ssa/ssa-thread-12.c: Same. + * gcc.dg/tree-ssa/ssa-thread-13.c: Same. + +2021-09-13 Patrick Palka <ppalka@redhat.com> + + PR c++/101764 + * g++.dg/cpp1z/constexpr-if35.C: New test. + +2021-09-13 Martin Liska <mliska@suse.cz> + + PR c++/101331 + * g++.dg/pr101331.C: New test. + +2021-09-13 Aldy Hernandez <aldyh@redhat.com> + + * gcc.dg/tree-ssa/ssa-dom-thread-7.c: Adjust for aarch64. + +2021-09-13 H.J. Lu <hjl.tools@gmail.com> + + PR target/101935 + * g++.target/i386/pr80566-1.C: Add + -mtune-ctrl=avx256_store_by_pieces. + * gcc.target/i386/pr100865-4a.c: Likewise. + * gcc.target/i386/pr100865-10a.c: Likewise. + * gcc.target/i386/pr90773-20.c: Likewise. + * gcc.target/i386/pr90773-21.c: Likewise. + * gcc.target/i386/pr90773-22.c: Likewise. + * gcc.target/i386/pr90773-23.c: Likewise. + * g++.target/i386/pr80566-2.C: Add + -mtune-ctrl=avx256_move_by_pieces. + * gcc.target/i386/eh_return-1.c: Likewise. + * gcc.target/i386/pr90773-26.c: Likewise. + * gcc.target/i386/pieces-memcpy-12.c: Replace -mtune=haswell + with -mtune-ctrl=avx256_move_by_pieces. + * gcc.target/i386/pieces-memcpy-15.c: Likewise. + * gcc.target/i386/pieces-memset-2.c: Replace -mtune=haswell + with -mtune-ctrl=avx256_store_by_pieces. + * gcc.target/i386/pieces-memset-5.c: Likewise. + * gcc.target/i386/pieces-memset-11.c: Likewise. + * gcc.target/i386/pieces-memset-14.c: Likewise. + * gcc.target/i386/pieces-memset-20.c: Likewise. + * gcc.target/i386/pieces-memset-23.c: Likewise. + * gcc.target/i386/pieces-memset-29.c: Likewise. + * gcc.target/i386/pieces-memset-30.c: Likewise. + * gcc.target/i386/pieces-memset-33.c: Likewise. + * gcc.target/i386/pieces-memset-34.c: Likewise. + * gcc.target/i386/pieces-memset-44.c: Likewise. + * gcc.target/i386/pieces-memset-37.c: Replace -mtune=generic + with -mtune-ctrl=avx256_store_by_pieces. + 2021-09-12 Iain Buclaw <ibuclaw@gdcproject.org> PR d/102185 diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-18.c b/gcc/testsuite/c-c++-common/gomp/atomic-18.c index b389c6a..a8ed3c7 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-18.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-18.c @@ -12,14 +12,12 @@ foo (int j) v = i; #pragma omp atomic acquire , write /* { dg-error "incompatible with 'acquire' clause" } */ i = v; - #pragma omp atomic capture hint (0) capture /* { dg-error "too many 'capture' clauses" "" { target c } } */ - /* { dg-error "too many atomic clauses" "" { target c++ } .-1 } */ + #pragma omp atomic capture hint (0) capture /* { dg-error "too many 'capture' clauses" } */ v = i = i + 1; #pragma omp atomic hint(j + 2) /* { dg-error "constant integer expression" } */ i = i + 1; #pragma omp atomic hint(f) /* { dg-error "integ" } */ i = i + 1; - #pragma omp atomic foobar /* { dg-error "expected 'read', 'write', 'update', 'capture', 'compare', 'weak', 'fail', 'seq_cst', 'acq_rel', 'release', 'relaxed' or 'hint' clause" "" { target c } } */ - /* { dg-error "expected 'read', 'write', 'update', 'capture', 'seq_cst', 'acq_rel', 'release', 'relaxed' or 'hint' clause" "" { target c++ } .-1 } */ - i = i + 1; /* { dg-error "expected end of line before" "" { target *-*-* } .-2 } */ + #pragma omp atomic foobar /* { dg-error "expected 'read', 'write', 'update', 'capture', 'compare', 'weak', 'fail', 'seq_cst', 'acq_rel', 'release', 'relaxed' or 'hint' clause" } */ + i = i + 1; /* { dg-error "expected end of line before" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-25.c b/gcc/testsuite/c-c++-common/gomp/atomic-25.c index a5196a5..653ef18 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-25.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-25.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ int x, r, z; double d, v; diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-26.c b/gcc/testsuite/c-c++-common/gomp/atomic-26.c index c7e65db..b7a4a1f 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-26.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-26.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ int x; double d; diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-27.c b/gcc/testsuite/c-c++-common/gomp/atomic-27.c index 3d61717..8f1e7e9 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-27.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-27.c @@ -1,5 +1,5 @@ /* PR middle-end/88968 */ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ struct __attribute__((packed)) S { unsigned int a : 16; diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-28.c b/gcc/testsuite/c-c++-common/gomp/atomic-28.c index 50cf223..853ae1c 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-28.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-28.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ /* { dg-additional-options "-O2 -fdump-tree-ompexp" } */ /* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 4, 5, 5\\\);" 1 "ompexp" { target sync_int_long } } } */ /* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 4, 4, 2\\\);" 1 "ompexp" { target sync_int_long } } } */ diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-29.c b/gcc/testsuite/c-c++-common/gomp/atomic-29.c index e574c48..1081e43 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-29.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-29.c @@ -1,10 +1,11 @@ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ /* { dg-additional-options "-O2 -fdump-tree-ompexp" } */ -/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 5, 5\\\);" 1 "ompexp" { target sync_int_long } } } */ -/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 4, 2\\\);" 1 "ompexp" { target sync_int_long } } } */ -/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 264, 5, 0\\\);" 1 "ompexp" { target sync_int_long } } } */ -/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 0, 0\\\);" 1 "ompexp" { target sync_int_long } } } */ -/* { dg-final { scan-tree-dump-not "__atomic_load_8 \\\(" "ompexp" { target sync_int_long } } } */ +/* { dg-additional-options "-march=pentium" { target ia32 } } */ +/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 5, 5\\\);" 1 "ompexp" { target sync_long_long } } } */ +/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 4, 2\\\);" 1 "ompexp" { target sync_long_long } } } */ +/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 264, 5, 0\\\);" 1 "ompexp" { target sync_long_long } } } */ +/* { dg-final { scan-tree-dump-times "\.ATOMIC_COMPARE_EXCHANGE \\\(\[^\n\r]*, 8, 0, 0\\\);" 1 "ompexp" { target sync_long_long } } } */ +/* { dg-final { scan-tree-dump-not "__atomic_load_8 \\\(" "ompexp" { target sync_long_long } } } */ double x; diff --git a/gcc/testsuite/c-c++-common/gomp/atomic-30.c b/gcc/testsuite/c-c++-common/gomp/atomic-30.c index f36de70..37a30bb 100644 --- a/gcc/testsuite/c-c++-common/gomp/atomic-30.c +++ b/gcc/testsuite/c-c++-common/gomp/atomic-30.c @@ -1,9 +1,9 @@ -/* { dg-do compile { target c } } */ +/* { dg-do compile } */ int x; double d, g; -double +void foo (int y, double e, long double f) { double v; @@ -21,18 +21,18 @@ foo (int y, double e, long double f) #pragma omp atomic compare if (d + e) { d = e; } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ #pragma omp atomic capture compare - { r = d >= e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare - { r = d <= e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare - { r = d > e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare - { r = d < e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare - { r = d != e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare - { r = d + e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" } */ - #pragma omp atomic capture compare + { r = d >= e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ + { r = d <= e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ + { r = d > e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ + { r = d < e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ + { r = d != e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ + { r = d + e; if (r) { d = f; } } /* { dg-error "expected '==', '<' or '>' comparison in 'if' condition" "" { target c } } */ + #pragma omp atomic capture compare /* { dg-error "invalid form of '#pragma omp atomic' before 'd'" "" { target c++ } .-1 } */ { r = d == e; if (r2) { d = f; } } /* { dg-error "invalid form of '#pragma omp atomic compare' before '\{' token" } */ #pragma omp atomic capture compare if (d > e) { d = e; } /* { dg-error "expected '==' comparison in 'if' condition" } */ @@ -97,41 +97,46 @@ foo (int y, double e, long double f) #pragma omp atomic compare x ^= 5; /* { dg-error "expected '=' before '\\\^=' token" } */ #pragma omp atomic compare - x = x + 3; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x - 5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = 2 * x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = 5 | x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x & ~5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x | 5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x >= 5 ? 5 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x <= 5 ? 5 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x != 5 ? 7 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = 5 == x ? 7 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x == 5 ? x : 7; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x == 5 ? 9 : 7; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x > 5 ? 6 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x < 5 ? 6 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x > 5 ? x : 6; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic compare - x = x < 5 ? x : 6; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ - #pragma omp atomic capture + x = x + 3; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before '\\\+' token" "" { target c++ } .-1 } */ + x = x - 5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before '-' token" "" { target c++ } .-1 } */ + x = 2 * x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic' before numeric constant" "" { target c++ } .-1 } */ + x = 5 | x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic' before numeric constant" "" { target c++ } .-1 } */ + x = x & ~5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before '\\\&' token" "" { target c++ } .-1 } */ + x = x | 5; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before '\\\|' token" "" { target c++ } .-1 } */ + x = x >= 5 ? 5 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid operator for '#pragma omp atomic' before '>=' token" "" { target c++ } .-1 } */ + x = x <= 5 ? 5 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid operator for '#pragma omp atomic' before '<=' token" "" { target c++ } .-1 } */ + x = x != 5 ? 7 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid operator for '#pragma omp atomic' before '!=' token" "" { target c++ } .-1 } */ + x = 5 == x ? 7 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic' before numeric constant" "" { target c++ } .-1 } */ + x = x == 5 ? x : 7; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ + x = x == 5 ? 9 : 7; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ + x = x > 5 ? 6 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ + x = x < 5 ? 6 : x; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ + x = x > 5 ? x : 6; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic compare /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ + x = x < 5 ? x : 6; /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + #pragma omp atomic capture /* { dg-error "invalid form of '#pragma omp atomic compare' before ';' token" "" { target c++ } .-1 } */ r = x == 5; /* { dg-error "invalid operator for '#pragma omp atomic' before '==' token" } */ #pragma omp atomic capture compare r = x == 5; /* { dg-error "expected '=' before '==' token" } */ #pragma omp atomic capture compare /* { dg-error "'#pragma omp atomic compare capture' with non-integral comparison result" } */ { v = x == 5; if (v) { x = 6; } } + #pragma omp atomic compare capture + { r2 = x; x = y; } /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" } */ + #pragma omp atomic compare capture + { r2 = x; x = y == 7 ? 12 : y; } /* { dg-error "invalid form of '#pragma omp atomic' before ';' token" "" { target c } } */ + /* { dg-error "invalid form of '#pragma omp atomic' before 'y'" "" { target c++ } .-1 } */ } diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-empty17.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-empty17.C new file mode 100644 index 0000000..86126da --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-empty17.C @@ -0,0 +1,21 @@ +// PR c++/102163 +// { dg-do compile { target c++11 } } + +struct O { + constexpr O(int) { } +}; + +union _Variadic_union { + constexpr _Variadic_union(int __arg) : _M_rest(__arg) { } + int _M_first; + O _M_rest; +}; + +constexpr _Variadic_union u(42); + +struct _Variant_storage { + constexpr _Variant_storage() : _M_u(42) {} + _Variadic_union _M_u; +}; + +constexpr _Variant_storage w; diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist125.C b/gcc/testsuite/g++.dg/cpp0x/initlist125.C new file mode 100644 index 0000000..49dee1c --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist125.C @@ -0,0 +1,12 @@ +// PR c++/102050 +// { dg-do compile { target c++11 } } + +#include <initializer_list> + +struct A { + A(std::initializer_list<int> = {}); +}; + +A x{0}; +A y{1, 2, 3}; +A z; diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist126.C b/gcc/testsuite/g++.dg/cpp0x/initlist126.C new file mode 100644 index 0000000..0a8fb99 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist126.C @@ -0,0 +1,17 @@ +// PR c++/102050 +// { dg-do compile { target c++11 } } + +#include <initializer_list> + +extern struct A a; + +struct A { + A(const A& = a); + A(std::initializer_list<int>) = delete; +}; + +void f(A); + +int main() { + f({}); // { dg-bogus "deleted" } +} diff --git a/gcc/testsuite/g++.dg/cpp0x/pr102305.C b/gcc/testsuite/g++.dg/cpp0x/pr102305.C new file mode 100644 index 0000000..e63adcf --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/pr102305.C @@ -0,0 +1,39 @@ +// PR c++/102305 +// { dg-do compile { target c++11 } } + +namespace std +{ + template<typename _Tp, _Tp __v> + struct integral_constant + { + static constexpr _Tp value = __v; + typedef integral_constant<_Tp, __v> type; + }; + + template<typename _Tp, _Tp __v> + constexpr _Tp integral_constant<_Tp, __v>::value; + + typedef integral_constant<bool, true> true_type; + typedef integral_constant<bool, false> false_type; + + template<bool __v> + using bool_constant = integral_constant<bool, __v>; + + template<typename _Tp, typename... _Args> + struct is_constructible + : public bool_constant<__is_constructible(_Tp, _Args...)> + { + }; +} + +template<typename> +struct A { + virtual ~A() = 0; +}; + +struct B { + virtual ~B() = 0; +}; + +static_assert(!std::is_constructible<A<int> >::value, ""); +static_assert(!std::is_constructible<B>::value, ""); diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1.C b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1.C new file mode 100644 index 0000000..80b48ba --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1.C @@ -0,0 +1,9 @@ +// PR c++/98486 +// { dg-do compile { target c++20 } } + +template<class T, class U> concept C = __is_same(T, U); + +template<C<int>> int v; + +template<> int v<int>; +template<> int v<char>; // { dg-error "match" } diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1a.C b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1a.C new file mode 100644 index 0000000..b12d37d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1a.C @@ -0,0 +1,14 @@ +// PR c++/98486 +// { dg-do compile { target c++20 } } + +template<class T, class U> concept C = __is_same(T, U); + +struct A { + template<C<int>> static int v; +}; + +template<> int A::v<int>; +template<> int A::v<char>; // { dg-error "match" } + +int x = A::v<int>; +int y = A::v<char>; // { dg-error "invalid" } diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1b.C b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1b.C new file mode 100644 index 0000000..37d7f0f --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-var-templ1b.C @@ -0,0 +1,15 @@ +// PR c++/98486 +// { dg-do compile { target c++20 } } + +template<class T, class U> concept C = __is_same(T, U); + +template<class T> +struct A { + template<C<T>> static int v; +}; + +template<> template<> int A<int>::v<int>; +template<> template<> int A<int>::v<char>; // { dg-error "match" } + +int x = A<int>::v<int>; +int y = A<int>::v<char>; // { dg-error "invalid" } diff --git a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C index 62263c0..8ea25e5 100644 --- a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C +++ b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C @@ -12,7 +12,11 @@ using namespace std; static void donkey () { - asm volatile ("fcpyd d9, %P0" : : "w" (1.2345) : "d9"); +#if __ARM_FP & 8 + asm volatile ("vmov.f64 d9, %P0" : : "w" (1.2345) : "d9"); +#else + asm volatile ("vmov.f32 s18, %0" : : "t" (1.2345f) : "s18"); +#endif throw 1; } diff --git a/gcc/testsuite/g++.dg/ext/conv2.C b/gcc/testsuite/g++.dg/ext/conv2.C new file mode 100644 index 0000000..baf2a43 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/conv2.C @@ -0,0 +1,13 @@ +// { dg-do compile { target c++11 } } +// { dg-additional-options "-fpermissive" } + +struct A { + A(int*, int); +}; + +void f(A); + +int main() { + const int n = 0; + f({&n, 42}); // { dg-warning "invalid conversion from 'const int\\*' to 'int\\*'" } +} diff --git a/gcc/testsuite/g++.dg/ext/flexary39.C b/gcc/testsuite/g++.dg/ext/flexary39.C new file mode 100644 index 0000000..8eb81f2 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/flexary39.C @@ -0,0 +1,65 @@ +// PR c++/88578 +// { dg-do run } +// { dg-options -Wno-pedantic } + +#define STR(s) #s +#define ASSERT(exp) \ + ((exp) ? (void)0 : (void)(__builtin_printf ("%s:%i: assertion %s failed\n", \ + __FILE__, __LINE__, STR(exp)), \ + __builtin_abort ())) + +typedef int int32_t __attribute__((mode (__SI__))); + +struct Ax { int32_t n, a[]; }; +struct AAx { int32_t i; Ax ax; }; + +int32_t i = 12345678; + +void +test () +{ + { + // OK. Does not assign any elements to flexible array. + Ax s = { 0 }; + ASSERT (s.n == 0); + } + { + // OK only for statically allocated objects, otherwise error. + static Ax s = { 0, { } }; + ASSERT (s.n == 0); + } + { + static Ax s = { 1, { 2 } }; + ASSERT (s.n == 1 && s.a [0] == 2); + } + { + static Ax s = { 2, { 3, 4 } }; + ASSERT (s.n = 2 && s.a [0] == 3 && s.a [1] == 4); + } + { + static Ax s = { 123, i }; + ASSERT (s.n == 123 && s.a [0] == i); + } + { + static Ax s = { 456, { i } }; + ASSERT (s.n == 456 && s.a [0] == i); + } + { + int32_t j = i + 1, k = j + 1; + static Ax s = { 3, { i, j, k } }; + ASSERT (s.n == 3 && s.a [0] == i && s.a [1] == j && s.a [2] == k); + } + + { + // OK. Does not assign any elements to flexible array. + AAx s = { 1, { 2 } }; + ASSERT (s.i == 1 && s.ax.n == 2); + } +} + +int +main () +{ + test (); + test (); +} diff --git a/gcc/testsuite/g++.dg/ext/flexary40.C b/gcc/testsuite/g++.dg/ext/flexary40.C new file mode 100644 index 0000000..ee824c2 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/flexary40.C @@ -0,0 +1,50 @@ +// PR c++/102295 +// { dg-do run } +// { dg-options "" } + +struct A { int a; int b[]; }; +struct B { B (); int k; }; +struct C { int l; B m[]; }; + +int x[4]; +A c = { 42, { ++x[0], ++x[1], ++x[2], ++x[3] } }; +A d = { 43, { 0, ++x[0], ++x[1], ++x[2], ++x[3] } }; +A e = { 44, { ++x[0], ++x[1], ++x[2], 17 } }; +A f = { 45 }; +C n = { 50, { B (), B () } }; +C o = { 51, {} }; + +int +main () +{ + static A g = { 46, { ++x[0], ++x[1], ++x[2], ++x[3] } }; + static A h = { 47, { 0, ++x[0], ++x[1], ++x[2], ++x[3] } }; + static A i = { 48, { ++x[0], ++x[1], ++x[2], 18 } }; + static A j = { 49 }; + if (c.a != 42 || c.b[0] != 1 || c.b[1] != 1 || c.b[2] != 1 || c.b[3] != 1) + __builtin_abort (); + if (d.a != 43 || d.b[0] != 0 || d.b[1] != 2 || d.b[2] != 2 || d.b[3] != 2 || d.b[4] != 2) + __builtin_abort (); + if (e.a != 44 || e.b[0] != 3 || e.b[1] != 3 || e.b[2] != 3 || e.b[3] != 17) + __builtin_abort (); + if (f.a != 45) + __builtin_abort (); + if (g.a != 46 || g.b[0] != 4 || g.b[1] != 4 || g.b[2] != 4 || g.b[3] != 3) + __builtin_abort (); + if (h.a != 47 || h.b[0] != 0 || h.b[1] != 5 || h.b[2] != 5 || h.b[3] != 5 || h.b[4] != 4) + __builtin_abort (); + if (i.a != 48 || i.b[0] != 6 || i.b[1] != 6 || i.b[2] != 6 || i.b[3] != 18) + __builtin_abort (); + if (j.a != 49) + __builtin_abort (); + if (n.l != 50 || n.m[0].k != 42 || n.m[1].k != 42) + __builtin_abort (); + if (o.l != 51) + __builtin_abort (); + if (x[0] != 6 || x[1] != 6 || x[2] != 6 || x[3] != 4) + __builtin_abort (); +} + +B::B () : k (42) +{ +} diff --git a/gcc/testsuite/g++.dg/gcov/gcov.py b/gcc/testsuite/g++.dg/gcov/gcov.py index a8c4ea9..5137f3a 100644 --- a/gcc/testsuite/g++.dg/gcov/gcov.py +++ b/gcc/testsuite/g++.dg/gcov/gcov.py @@ -5,6 +5,9 @@ import os def gcov_from_env(): # return parsed JSON content a GCOV_PATH file - json_filename = os.environ['GCOV_PATH'] + '.gcov.json.gz' + json_filename = os.environ['GCOV_PATH'] + # strip extension + json_filename = json_filename[:json_filename.rindex('.')] + json_filename += '.gcov.json.gz' json_data = gzip.open(json_filename).read() return json.loads(json_data) diff --git a/gcc/testsuite/g++.dg/gomp/atomic-20.C b/gcc/testsuite/g++.dg/gomp/atomic-20.C new file mode 100644 index 0000000..cb7a37b --- /dev/null +++ b/gcc/testsuite/g++.dg/gomp/atomic-20.C @@ -0,0 +1,104 @@ +// { dg-do compile } + +int x, r, z; +double d, v; +long double ld; + +template <int N> +void +foo (int y, double e, long double f) +{ + #pragma omp atomic compare update seq_cst + x = x > y ? y : x; + #pragma omp atomic compare relaxed + d = e > d ? e : d; + #pragma omp atomic compare + d = f < d ? f : d; + #pragma omp atomic compare seq_cst fail(relaxed) + x = 12U < x ? 12U : x; + #pragma omp atomic compare + x = x == 7 ? 24 : x; + #pragma omp atomic compare + x = x == 123UL ? 256LL : x; + #pragma omp atomic compare + ld = ld == f ? f + 5.0L : ld; + #pragma omp atomic compare + if (x == 9) { x = 5; } + #pragma omp atomic compare + if (x > 5) { x = 5; } + #pragma omp atomic compare + if (7 > x) { x = 7; } + #pragma omp atomic compare update capture seq_cst fail(acquire) + v = d = f > d ? f : d; + #pragma omp atomic update capture compare + v = x = x < 24ULL ? 24ULL : x; + #pragma omp atomic compare, capture, update + v = x = x == e ? f : x; + #pragma omp atomic capture compare + { v = d; if (d > e) { d = e; } } + #pragma omp atomic compare capture + { if (e < d) { d = e; } v = d; } + #pragma omp atomic compare capture + { y = x; if (x == 42) { x = 7; } } + #pragma omp atomic capture compare weak + { if (x == 42) { x = 7; } y = x; } + #pragma omp atomic capture compare fail(seq_cst) + if (d == 8.0) { d = 16.0; } else { v = d; } + #pragma omp atomic capture compare + { r = x == 8; if (r) { x = 24; } } + #pragma omp atomic compare capture + { r = x == y; if (r) { x = y + 6; } else { z = x; } } +} + +template <typename I, typename D, typename LD> +void +bar (I &x, I &r, I &z, D &d, D &v, LD &ld, I y, D e, LD f) +{ + #pragma omp atomic compare update seq_cst + x = x > y ? y : x; + #pragma omp atomic compare relaxed + d = e > d ? e : d; + #pragma omp atomic compare + d = f < d ? f : d; + #pragma omp atomic compare seq_cst fail(relaxed) + x = 12U < x ? 12U : x; + #pragma omp atomic compare + x = x == 7 ? 24 : x; + #pragma omp atomic compare + x = x == 123UL ? 256LL : x; + #pragma omp atomic compare + ld = ld == f ? f + 5.0L : ld; + #pragma omp atomic compare + if (x == 9) { x = 5; } + #pragma omp atomic compare + if (x > 5) { x = 5; } + #pragma omp atomic compare + if (7 > x) { x = 7; } + #pragma omp atomic compare update capture seq_cst fail(acquire) + v = d = f > d ? f : d; + #pragma omp atomic update capture compare + v = x = x < 24ULL ? 24ULL : x; + #pragma omp atomic compare, capture, update + v = x = x == e ? f : x; + #pragma omp atomic capture compare + { v = d; if (d > e) { d = e; } } + #pragma omp atomic compare capture + { if (e < d) { d = e; } v = d; } + #pragma omp atomic compare capture + { y = x; if (x == 42) { x = 7; } } + #pragma omp atomic capture compare weak + { if (x == 42) { x = 7; } y = x; } + #pragma omp atomic capture compare fail(seq_cst) + if (d == 8.0) { d = 16.0; } else { v = d; } + #pragma omp atomic capture compare + { r = x == 8; if (r) { x = 24; } } + #pragma omp atomic compare capture + { r = x == y; if (r) { x = y + 6; } else { z = x; } } +} + +void +baz (int y, double e, long double f) +{ + foo <0> (y, e, f); + bar (x, r, z, d, v, ld, y, e, f); +} diff --git a/gcc/testsuite/g++.dg/gomp/atomic-5.C b/gcc/testsuite/g++.dg/gomp/atomic-5.C index 78f6344..e2fd591 100644 --- a/gcc/testsuite/g++.dg/gomp/atomic-5.C +++ b/gcc/testsuite/g++.dg/gomp/atomic-5.C @@ -23,7 +23,7 @@ void f1(void) #pragma omp atomic bar() += 1; /* { dg-error "lvalue required" } */ #pragma omp atomic a /* { dg-error "expected end of line" } */ - x++; /* { dg-error "expected 'read', 'write', 'update', 'capture', 'seq_cst', 'acq_rel', 'release', 'relaxed' or 'hint' clause" "" { target *-*-* } .-1 } */ + x++; /* { dg-error "expected 'read', 'write', 'update', 'capture', 'compare', 'weak', 'fail', 'seq_cst', 'acq_rel', 'release', 'relaxed' or 'hint' clause" "" { target *-*-* } .-1 } */ #pragma omp atomic ; /* { dg-error "expected primary-expression" } */ #pragma omp atomic diff --git a/gcc/testsuite/g++.dg/pr102360.C b/gcc/testsuite/g++.dg/pr102360.C new file mode 100644 index 0000000..fdf9e08 --- /dev/null +++ b/gcc/testsuite/g++.dg/pr102360.C @@ -0,0 +1,54 @@ +// { dg-do compile } +// { dg-options "-fno-tree-dse -O1 -ftrivial-auto-var-init=pattern" } + +class A; +template <typename _Tp, int m, int n> class B { +public: + _Tp val[m * n]; +}; +class C { +public: + C(A); +}; +struct D { + D(); + unsigned long &operator[](int); + unsigned long *p; +}; +class A { +public: + template <typename _Tp, int m, int n> A(const B<_Tp, m, n> &, bool); + int rows, cols; + unsigned char *data; + unsigned char *datastart; + unsigned char *dataend; + unsigned char *datalimit; + D step; +}; +template <typename _Tp, int m, int n> +A::A(const B<_Tp, m, n> &p1, bool) + : rows(m), cols(n) { + step[0] = cols * sizeof(_Tp); + datastart = data = (unsigned char *)p1.val; + datalimit = dataend = datastart + rows * step[0]; +} +class F { +public: + static void compute(C); + template <typename _Tp, int m, int n, int nm> + static void compute(const B<_Tp, m, n> &, B<_Tp, nm, 1> &, B<_Tp, m, nm> &, + B<_Tp, n, nm> &); +}; +D::D() {} +unsigned long &D::operator[](int p1) { return p[p1]; } +template <typename _Tp, int m, int n, int nm> +void F::compute(const B<_Tp, m, n> &, B<_Tp, nm, 1> &, B<_Tp, m, nm> &, + B<_Tp, n, nm> &p4) { + A a(p4, false); + compute(a); +} +void fn1() { + B<double, 4, 4> b, c, e; + B<double, 4, 1> d; + F::compute(b, d, c, e); +} diff --git a/gcc/testsuite/g++.dg/rtti/undeclared1.C b/gcc/testsuite/g++.dg/rtti/undeclared1.C new file mode 100644 index 0000000..9594c22 --- /dev/null +++ b/gcc/testsuite/g++.dg/rtti/undeclared1.C @@ -0,0 +1,5 @@ +// PR c++/48396 + +namespace std { + type_info *p; // { dg-error "type_info" } +} diff --git a/gcc/testsuite/g++.dg/template/conv17.C b/gcc/testsuite/g++.dg/template/conv17.C index ba012c9..f0f10f2 100644 --- a/gcc/testsuite/g++.dg/template/conv17.C +++ b/gcc/testsuite/g++.dg/template/conv17.C @@ -53,4 +53,11 @@ concept D = requires (const T t) { }; static_assert(D<C>); + +// Test that when there's no strictly viable candidate and we're in a +// SFINAE context, we still stop at the first bad argument conversion. +template<class T> +concept E = requires { T().h(nullptr); }; + +static_assert(!E<C>); #endif diff --git a/gcc/testsuite/g++.target/i386/pr102295.C b/gcc/testsuite/g++.target/i386/pr102295.C new file mode 100644 index 0000000..09efc3c --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr102295.C @@ -0,0 +1,12 @@ +// PR c++/102295 +// { dg-do compile { target *-*-linux* } } +// { dg-options "-Wno-pedantic" } + +struct S { + int a; + int b[]; +} S; + +struct S s = { 1, { 2, 3 } }; + +/* { dg-final { scan-assembler ".size\[\t \]*s, 12" } } */ diff --git a/gcc/testsuite/gcc.dg/Wint-in-bool-context-4.c b/gcc/testsuite/gcc.dg/Wint-in-bool-context-4.c new file mode 100644 index 0000000..0e96dd7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/Wint-in-bool-context-4.c @@ -0,0 +1,35 @@ +/* PR c/102245 */ +/* { dg-options "-Wint-in-bool-context" } */ +/* { dg-do compile } */ + +_Bool test1(_Bool x) +{ + return !(x << 0); /* { dg-warning "boolean context" } */ +} + +_Bool test2(_Bool x) +{ + return !(x << 1); /* { dg-warning "boolean context" } */ +} + +_Bool test3(_Bool x, int y) +{ + return !(x << y); /* { dg-warning "boolean context" } */ +} + +_Bool test4(int x, int y) +{ + return !(x << y); /* { dg-warning "boolean context" } */ +} + +_Bool test5(int x, int y) +{ + return !((x << y) << 0); /* { dg-warning "boolean context" } */ +} + +int test6(_Bool x) +{ + int v = 0; + return (v & ~1L) | (1L & (x << 0)); /* { dg-bogus "boolean context" } */ +} + diff --git a/gcc/testsuite/gcc.dg/vect/pr102318.c b/gcc/testsuite/gcc.dg/vect/pr102318.c new file mode 100644 index 0000000..cc58efa --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr102318.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ + +void +vec_slp_int16_t (short int *restrict a, short int *restrict b, int n) +{ + short int x0 = b[0]; + short int x1 = b[1]; + short int x2 = b[2]; + short int x3 = b[3]; + for (int i = 0; i < n; ++i) + { + x0 += a[i * 4]; + x1 += a[i * 4 + 1]; + x2 += a[i * 4 + 2]; + x3 += a[i * 4 + 3]; + } + b[0] = x0; + b[1] = x1; + b[2] = x2; + b[3] = x3; +} diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index d9aa8a7..add3e0c 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -686,25 +686,85 @@ #define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E) /* avx512fp16intrin.h */ -#define __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vcmpph_v32hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v32hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpph_v32hf_mask_round(A, B, 1, D, 8) -#define __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_addph512_mask_round(A, B, C, D, E) __builtin_ia32_addph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subph512_mask_round(A, B, C, D, E) __builtin_ia32_subph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulph512_mask_round(A, B, C, D, E) __builtin_ia32_mulph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divph512_mask_round(A, B, C, D, E) __builtin_ia32_divph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_addsh_mask_round(A, B, C, D, E) __builtin_ia32_addsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subsh_mask_round(A, B, C, D, E) __builtin_ia32_subsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulsh_mask_round(A, B, C, D, E) __builtin_ia32_mulsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divsh_mask_round(A, B, C, D, E) __builtin_ia32_divsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxph512_mask_round(A, B, C, D, E) __builtin_ia32_maxph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minph512_mask_round(A, B, C, D, E) __builtin_ia32_minph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxsh_mask_round(A, B, C, D, E) __builtin_ia32_maxsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minsh_mask_round(A, B, C, D, E) __builtin_ia32_minsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_cmpph512_mask(A, B, C, D) __builtin_ia32_cmpph512_mask(A, B, 1, D) +#define __builtin_ia32_cmpph512_mask_round(A, B, C, D, E) __builtin_ia32_cmpph512_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_cmpsh_mask_round(A, B, C, D, E) __builtin_ia32_cmpsh_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_sqrtph512_mask_round(C, A, B, D) __builtin_ia32_sqrtph512_mask_round(C, A, B, 8) +#define __builtin_ia32_sqrtsh_mask_round(D, C, A, B, E) __builtin_ia32_sqrtsh_mask_round(D, C, A, B, 8) +#define __builtin_ia32_scalefph512_mask_round(A, B, C, D, E) __builtin_ia32_scalefph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_scalefsh_mask_round(A, B, C, D, E) __builtin_ia32_scalefsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_reduceph512_mask_round(A, B, C, D, E) __builtin_ia32_reduceph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_reduceph128_mask(A, B, C, D) __builtin_ia32_reduceph128_mask(A, 123, C, D) +#define __builtin_ia32_reduceph256_mask(A, B, C, D) __builtin_ia32_reduceph256_mask(A, 123, C, D) +#define __builtin_ia32_reducesh_mask_round(A, B, C, D, E, F) __builtin_ia32_reducesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_rndscaleph512_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_rndscaleph128_mask(A, B, C, D) __builtin_ia32_rndscaleph128_mask(A, 123, C, D) +#define __builtin_ia32_rndscaleph256_mask(A, B, C, D) __builtin_ia32_rndscaleph256_mask(A, 123, C, D) +#define __builtin_ia32_rndscalesh_mask_round(A, B, C, D, E, F) __builtin_ia32_rndscalesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_fpclassph512_mask(A, D, C) __builtin_ia32_fpclassph512_mask(A, 1, C) +#define __builtin_ia32_fpclasssh_mask(A, D, U) __builtin_ia32_fpclasssh_mask(A, 1, U) +#define __builtin_ia32_getexpph512_mask(A, B, C, D) __builtin_ia32_getexpph512_mask(A, B, C, 8) +#define __builtin_ia32_getexpsh_mask_round(A, B, C, D, E) __builtin_ia32_getexpsh_mask_round(A, B, C, D, 4) +#define __builtin_ia32_getmantph512_mask(A, F, C, D, E) __builtin_ia32_getmantph512_mask(A, 1, C, D, 8) +#define __builtin_ia32_getmantsh_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsh_mask_round(A, B, 1, W, U, 4) +#define __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2si32_round(A, B) __builtin_ia32_vcvtsh2si32_round(A, 8) +#define __builtin_ia32_vcvtsh2si64_round(A, B) __builtin_ia32_vcvtsh2si64_round(A, 8) +#define __builtin_ia32_vcvtsh2usi32_round(A, B) __builtin_ia32_vcvtsh2usi32_round(A, 8) +#define __builtin_ia32_vcvtsh2usi64_round(A, B) __builtin_ia32_vcvtsh2usi64_round(A, 8) +#define __builtin_ia32_vcvttsh2si32_round(A, B) __builtin_ia32_vcvttsh2si32_round(A, 8) +#define __builtin_ia32_vcvttsh2si64_round(A, B) __builtin_ia32_vcvttsh2si64_round(A, 8) +#define __builtin_ia32_vcvttsh2usi32_round(A, B) __builtin_ia32_vcvttsh2usi32_round(A, 8) +#define __builtin_ia32_vcvttsh2usi64_round(A, B) __builtin_ia32_vcvttsh2usi64_round(A, 8) +#define __builtin_ia32_vcvtsi2sh32_round(A, B, C) __builtin_ia32_vcvtsi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtsi2sh64_round(A, B, C) __builtin_ia32_vcvtsi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh32_round(A, B, C) __builtin_ia32_vcvtusi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh64_round(A, B, C) __builtin_ia32_vcvtusi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, 8) /* avx512fp16vlintrin.h */ -#define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v16hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v16hf_mask(A, B, 1, D) +#define __builtin_ia32_cmpph128_mask(A, B, C, D) __builtin_ia32_cmpph128_mask(A, B, 1, D) +#define __builtin_ia32_cmpph256_mask(A, B, C, D) __builtin_ia32_cmpph256_mask(A, B, 1, D) +#define __builtin_ia32_fpclassph256_mask(A, D, C) __builtin_ia32_fpclassph256_mask(A, 1, C) +#define __builtin_ia32_fpclassph128_mask(A, D, C) __builtin_ia32_fpclassph128_mask(A, 1, C) +#define __builtin_ia32_getmantph256_mask(A, E, C, D) __builtin_ia32_getmantph256_mask(A, 1, C, D) +#define __builtin_ia32_getmantph128_mask(A, E, C, D) __builtin_ia32_getmantph128_mask(A, 1, C, D) /* vpclmulqdqintrin.h */ #define __builtin_ia32_vpclmulqdq_v4di(A, B, C) __builtin_ia32_vpclmulqdq_v4di(A, B, 1) diff --git a/gcc/testsuite/gcc.target/i386/avx-covert-1.c b/gcc/testsuite/gcc.target/i386/avx-covert-1.c new file mode 100644 index 0000000..b6c794e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-covert-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency,^sse_partial_reg_converts_dependency" } */ + +extern float f; +extern double d; +extern int i; + +void +foo (void) +{ + d = f; + f = i; +} + +/* { dg-final { scan-assembler "vcvtss2sd" } } */ +/* { dg-final { scan-assembler "vcvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "vcvtps2pd" } } */ +/* { dg-final { scan-assembler-not "vcvtdq2ps" } } */ +/* { dg-final { scan-assembler-not "vxorps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-fp-covert-1.c b/gcc/testsuite/gcc.target/i386/avx-fp-covert-1.c new file mode 100644 index 0000000..c40c48b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-fp-covert-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency" } */ + +extern float f; +extern double d; + +void +foo (void) +{ + d = f; +} + +/* { dg-final { scan-assembler "vcvtss2sd" } } */ +/* { dg-final { scan-assembler-not "vcvtps2pd" } } */ +/* { dg-final { scan-assembler-not "vxorps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx-int-covert-1.c b/gcc/testsuite/gcc.target/i386/avx-int-covert-1.c new file mode 100644 index 0000000..01bb64e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-int-covert-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=^sse_partial_reg_converts_dependency" } */ + +extern float f; +extern int i; + +void +foo (void) +{ + f = i; +} + +/* { dg-final { scan-assembler "vcvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "vxorps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-1c.c b/gcc/testsuite/gcc.target/i386/avx512fp16-1c.c index 49fc2aa..b41a90b 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-1c.c +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-1c.c @@ -1,8 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-mavx512fp16 -O2" } */ -/* { dg-final { scan-assembler-times "(?:vmovsh|vmovw)" 2 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "vpinsrw" 1 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "vpinsrw" 2 { target { ia32 } } } } */ +/* { dg-final { scan-assembler-times "vmovsh" 1 } } */ +/* { dg-final { scan-assembler-times "vpblendw" 1 } } */ +/* { dg-final { scan-assembler "vpbroadcastw" } } */ typedef _Float16 __v8hf __attribute__ ((__vector_size__ (16))); typedef _Float16 __m128h __attribute__ ((__vector_size__ (16), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h index 5d3539b..ce3cfdc 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h @@ -17,6 +17,7 @@ /* Useful macros. */ #define NOINLINE __attribute__((noinline,noclone)) #define _ROUND_NINT (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC) +#define _ROUND_CUR 8 #define AVX512F_MAX_ELEM 512 / 32 /* Structure for _Float16 emulation */ @@ -24,18 +25,28 @@ typedef union { __m512 zmm; __m512h zmmh; + __m512i zmmi; + __m512d zmmd; __m256 ymm[2]; __m256h ymmh[2]; __m256i ymmi[2]; + __m256d ymmd[2]; __m128h xmmh[4]; + __m128 xmm[4]; + __m128i xmmi[4]; + __m128d xmmd[4]; unsigned short u16[32]; unsigned int u32[16]; + int i32[16]; + long long s64[8]; + unsigned long long u64[8]; + double f64[8]; float f32[16]; _Float16 f16[32]; } V512; /* Global variables. */ -V512 src1, src2, src3; +V512 src1, src2, src3, src3f; int n_errs = 0; /* Helper function for packing/unpacking ph operands. */ @@ -160,12 +171,16 @@ init_src() int i; for (i = 0; i < AVX512F_MAX_ELEM; i++) { - v1.f32[i] = -i + 1; - v2.f32[i] = i * 0.5f; - v3.f32[i] = i * 2.5f; - v4.f32[i] = i - 0.5f; + v1.f32[i] = i + 1; + v2.f32[i] = i * 0.5f; + v3.f32[i] = i * 1.5f; + v4.f32[i] = i - 0.5f; - src3.u32[i] = (i + 1) * 10; + src3.u32[i] = (i + 1) * 10; + } + + for (i = 0; i < 8; i++) { + src3f.f64[i] = (i + 1) * 7.5; } src1 = pack_twops_2ph(v1, v2); @@ -215,30 +230,50 @@ init_dest(V512 * res, V512 * exp) #if AVX512F_LEN == 256 #undef HF #undef SF +#undef SI +#undef DF +#undef H_HF #undef NET_MASK -#undef MASK_VALUE +#undef MASK_VALUE +#undef HALF_MASK #undef ZMASK_VALUE #define NET_MASK 0xffff #define MASK_VALUE 0xcccc #define ZMASK_VALUE 0xfcc1 +#define HALF_MASK 0xcc #define HF(x) x.ymmh[0] +#define H_HF(x) x.xmmh[0] #define SF(x) x.ymm[0] +#define DF(x) x.ymmd[0] +#define SI(x) x.ymmi[0] #elif AVX512F_LEN == 128 #undef HF #undef SF +#undef DF +#undef SI +#undef H_HF #undef NET_MASK #undef MASK_VALUE #undef ZMASK_VALUE +#undef HALF_MASK #define NET_MASK 0xff #define MASK_VALUE 0xcc +#define HALF_MASK MASK_VALUE #define ZMASK_VALUE 0xc1 #define HF(x) x.xmmh[0] #define SF(x) x.xmm[0] +#define DF(x) x.xmmd[0] +#define SI(x) x.xmmi[0] +#define H_HF(x) x.xmmh[0] #else #define NET_MASK 0xffffffff #define MASK_VALUE 0xcccccccc #define ZMASK_VALUE 0xfcc1fcc1 +#define HALF_MASK 0xcccc #define HF(x) x.zmmh #define SF(x) x.zmm +#define DF(x) x.zmmd +#define SI(x) x.zmmi +#define H_HF(x) x.ymmh[0] #endif diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-1.c b/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-1.c new file mode 100644 index 0000000..cf0cc74 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-1.c @@ -0,0 +1,44 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +void +test_512 (void) +{ + V512 res; + + res.ymmh[0] = _mm512_castph512_ph256 (src1.zmmh); + check_results (&res, &src1, 16, "_mm512_castph512_ph256"); + + res.xmmh[0] = _mm512_castph512_ph128 (src1.zmmh); + check_results (&res, &src1, 8, "_mm512_castph512_ph128"); + + res.zmmh = _mm512_castph256_ph512 (src1.ymmh[0]); + check_results (&res, &src1, 16, "_mm512_castph256_ph512"); + + res.zmmh = _mm512_castph128_ph512 (src1.xmmh[0]); + check_results (&res, &src1, 8, "_mm512_castph128_ph512"); + + res.zmm = _mm512_castph_ps (src1.zmmh); + check_results (&res, &src1, 32, "_mm512_castph_ps"); + + res.zmmd = _mm512_castph_pd (src1.zmmh); + check_results (&res, &src1, 32, "_mm512_castph_pd"); + + res.zmmi = _mm512_castph_si512 (src1.zmmh); + check_results (&res, &src1, 32, "_mm512_castph_si512"); + + res.zmmh = _mm512_castps_ph (src1.zmm); + check_results (&res, &src1, 32, "_mm512_castps_ph"); + + res.zmmh = _mm512_castpd_ph (src1.zmmd); + check_results (&res, &src1, 32, "_mm512_castpd_ph"); + + res.zmmh = _mm512_castsi512_ph (src1.zmmi); + check_results (&res, &src1, 32, "_mm512_castsi512_ph"); + + if (n_errs != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-2.c b/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-2.c new file mode 100644 index 0000000..a29f1db --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-typecast-2.c @@ -0,0 +1,43 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512f-check.h" + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); + +void +do_test (void) +{ + union512i_d zero; + union512h ad; + union256h b,bd; + union128h c; + + int i; + + for (i = 0; i < 16; i++) + { + b.a[i] = 65.43f + i; + zero.a[i] = 0; + } + + for (i = 0; i < 8; i++) + { + c.a[i] = 32.01f + i; + } + + ad.x = _mm512_zextph256_ph512 (b.x); + if (memcmp (ad.a, b.a, 32) + || memcmp (&ad.a[16], &zero.a, 32)) + abort (); + + ad.x = _mm512_zextph128_ph512 (c.x); + if (memcmp (ad.a, c.a, 16) + || memcmp (&ad.a[8], &zero.a, 48)) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c new file mode 100644 index 0000000..45697d94 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi32_ph (x1); + res1 = _mm512_mask_cvtepi32_ph (res, m16, x2); + res2 = _mm512_maskz_cvtepi32_ph (m16, x3); + res = _mm512_cvt_roundepi32_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepi32_ph (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundepi32_ph (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c new file mode 100644 index 0000000..a2bb56c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) + +void NOINLINE +EMULATE(cvtd2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u32[i]; + } + } + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvtepi32_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepi32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvtepi32_ph) (H_HF(res), HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepi32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvtepi32_ph) (HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepi32_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvt_roundepi32_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepi32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvt_roundepi32_ph) (H_HF(res), HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepi32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvt_roundepi32_ph) (HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepi32_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1a.c new file mode 100644 index 0000000..8f74405 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtpd2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, res1, res2; +volatile __m512d x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtpd_ph (x1); + res1 = _mm512_mask_cvtpd_ph (res, m8, x2); + res2 = _mm512_maskz_cvtpd_ph (m8, x3); + res = _mm512_cvt_roundpd_ph (x1, 4); + res1 = _mm512_mask_cvt_roundpd_ph (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundpd_ph (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1b.c new file mode 100644 index 0000000..dde364b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtpd2ph-1b.c @@ -0,0 +1,82 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 64) + +void NOINLINE +EMULATE(cvtpd2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.f64[i]; + } + } + *dest = pack_twops_2ph(v5, v5); + for (i = n_el; i < 8; i++) + dest->u16[i] = 0; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvtpd_ph) (DF(src3f)); + CHECK_RESULT (&res, &exp, 8, _cvtpd_ph); + + init_dest(&res, &exp); + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvtpd_ph) (res.xmmh[0], 0xcc, + DF(src3f)); + CHECK_RESULT (&res, &exp, 8, _mask_cvtpd_ph); + + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvtpd_ph) (0xf1, DF(src3f)); + CHECK_RESULT (&res, &exp, 8, _maskz_cvtpd_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvt_roundpd_ph) (DF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _cvt_roundpd_ph); + + init_dest(&res, &exp); + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvt_roundpd_ph) (res.xmmh[0], 0xcc, + DF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _mask_cvt_roundpd_ph); + + EMULATE(cvtpd2_ph)(&exp, src3f, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvt_roundpd_ph) (0xf1, DF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _maskz_cvt_roundpd_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c new file mode 100644 index 0000000..31a5639 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi32 (x1); + res1 = _mm512_mask_cvtph_epi32 (res, m16, x2); + res2 = _mm512_maskz_cvtph_epi32 (m16, x3); + res = _mm512_cvt_roundph_epi32 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi32 (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c new file mode 100644 index 0000000..80a8582 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi32); +#endif + + if (n_errs != 0) + abort (); +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1a.c new file mode 100644 index 0000000..b7bb3b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512d res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_pd (x1); + res1 = _mm512_mask_cvtph_pd (res, m8, x2); + res2 = _mm512_maskz_cvtph_pd (m8, x3); + res = _mm512_cvt_roundph_pd (x1, 4); + res1 = _mm512_mask_cvt_roundph_pd (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundph_pd (m8, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1b.c new file mode 100644 index 0000000..c20888b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2pd-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_pd) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.f64[i] = v1.f32[i]; + } + } + + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_pd)(&exp, src1, NET_MASK, 0); + DF(res) = INTRINSIC (_cvtph_pd) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_pd); + + init_dest(&res, &exp); + EMULATE(cvtph2_pd)(&exp, src1, 0xcc, 0); + DF(res) = INTRINSIC (_mask_cvtph_pd) (DF(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_pd); + + EMULATE(cvtph2_pd)(&exp, src1, 0xc1, 1); + DF(res) = INTRINSIC (_maskz_cvtph_pd) (0xc1, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_pd); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_pd)(&exp, src1, NET_MASK, 0); + DF(res) = INTRINSIC (_cvt_roundph_pd) (src1.xmmh[0], _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_pd); + + init_dest(&res, &exp); + EMULATE(cvtph2_pd)(&exp, src1, 0xcc, 0); + DF(res) = INTRINSIC (_mask_cvt_roundph_pd) (DF(res), 0xcc, src1.xmmh[0], _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_pd); + + EMULATE(cvtph2_pd)(&exp, src1, 0xc1, 1); + DF(res) = INTRINSIC (_maskz_cvt_roundph_pd) (0xc1, src1.xmmh[0], _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_pd); +#endif + + if (n_errs != 0) { + abort (); +} +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1a.c new file mode 100644 index 0000000..c79549f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512 res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtxph_ps (x1); + res1 = _mm512_mask_cvtxph_ps (res, m16, x2); + res2 = _mm512_maskz_cvtxph_ps (m16, x3); + res = _mm512_cvtx_roundph_ps (x1, 4); + res1 = _mm512_mask_cvtx_roundph_ps (res, m16, x2, 8); + res2 = _mm512_maskz_cvtx_roundph_ps (m16, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1b.c new file mode 100644 index 0000000..a2f20c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2psx-1b.c @@ -0,0 +1,81 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) +#define CHECK_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtxph2_ps) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.f32[i] = v1.f32[i]; + } + } + + for (i = n_el; i < 16; i++) + v5.u32[i] = 0; + + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xffff, 0); + SF(res) = INTRINSIC (_cvtxph_ps) (H_HF(src1)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _cvtxph_ps); + + init_dest(&res, &exp); + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xcc, 0); + SF(res) = INTRINSIC (_mask_cvtxph_ps) (SF(res), 0xcc, H_HF(src1)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _mask_cvtxph_ps); + + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xc1, 1); + SF(res) = INTRINSIC (_maskz_cvtxph_ps) (0xc1, H_HF(src1)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _maskz_cvtxph_ps); + +#if AVX512F_LEN == 512 + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xffff, 0); + SF(res) = INTRINSIC (_cvtx_roundph_ps) (H_HF(src1), _ROUND_CUR); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _cvtx_roundph_ps); + + init_dest(&res, &exp); + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xcc, 0); + SF(res) = INTRINSIC (_mask_cvtx_roundph_ps) (SF(res), 0xcc, H_HF(src1), _ROUND_CUR); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _mask_cvtx_roundph_ps); + + EMULATE(cvtxph2_ps)(&exp, src1, N_ELEMS, 0xc1, 1); + SF(res) = INTRINSIC (_maskz_cvtx_roundph_ps) (0xc1, H_HF(src1), _ROUND_CUR); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _maskz_cvtx_roundph_ps); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c new file mode 100644 index 0000000..d80ee61 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi64 (x1); + res1 = _mm512_mask_cvtph_epi64 (res, m8, x2); + res2 = _mm512_maskz_cvtph_epi64 (m8, x3); + res = _mm512_cvt_roundph_epi64 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi64 (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c new file mode 100644 index 0000000..42b21cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi64) (0xfa, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi64) (0xfa, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c new file mode 100644 index 0000000..b4a833a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu32 (x1); + res1 = _mm512_mask_cvtph_epu32 (res, m16, x2); + res2 = _mm512_maskz_cvtph_epu32 (m16, x3); + res = _mm512_cvt_roundph_epu32 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu32 (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c new file mode 100644 index 0000000..15fa0ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu32); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c new file mode 100644 index 0000000..b408779 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu64 (x1); + res1 = _mm512_mask_cvtph_epu64 (res, m8, x2); + res2 = _mm512_maskz_cvtph_epu64 (m8, x3); + res = _mm512_cvt_roundph_epu64 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu64 (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c new file mode 100644 index 0000000..7f34772 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu64) (0xfc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu64) (0xfc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c new file mode 100644 index 0000000..2622745 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu16 (x1); + res1 = _mm512_mask_cvtph_epu16 (res, m32, x2); + res2 = _mm512_maskz_cvtph_epu16 (m32, x3); + res = _mm512_cvt_roundph_epu16 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu16 (m32, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c new file mode 100644 index 0000000..437a1f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu16); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c new file mode 100644 index 0000000..bcaa744 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi16 (x1); + res1 = _mm512_mask_cvtph_epi16 (res, m32, x2); + res2 = _mm512_maskz_cvtph_epi16 (m32, x3); + res = _mm512_cvt_roundph_epi16 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi16 (m32, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c new file mode 100644 index 0000000..dfa2052 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c @@ -0,0 +1,83 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res, exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi16); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1a.c new file mode 100644 index 0000000..cb957f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res, res1, res2; +volatile __m512 x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtxps_ph (x1); + res1 = _mm512_mask_cvtxps_ph (res, m16, x2); + res2 = _mm512_maskz_cvtxps_ph (m16, x3); + res = _mm512_cvtx_roundps_ph (x1, 4); + res1 = _mm512_mask_cvtx_roundps_ph (res, m16, x2, 8); + res2 = _mm512_maskz_cvtx_roundps_ph (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1b.c new file mode 100644 index 0000000..e316e76 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtps2ph-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) +#define CHECK_ELEMS (AVX512F_LEN_HALF / 16) + +void NOINLINE +EMULATE(cvtxps2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.f32[i]; + } + } + *dest = pack_twops_2ph(v5, v5); + for (i = n_el; i < 16; i++) + dest->u16[i] = 0; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvtxps_ph) (SF(src3f)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _cvtxps_ph); + + init_dest(&res, &exp); + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, 0xcc, 0); + H_HF(res) = INTRINSIC (_mask_cvtxps_ph) (H_HF(res), 0xcc, + SF(src3f)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _mask_cvtxps_ph); + + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, 0xf1, 1); + H_HF(res) = INTRINSIC (_maskz_cvtxps_ph) (0xf1, SF(src3f)); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _maskz_cvtxps_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvtx_roundps_ph) (SF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _cvtx_roundps_ph); + + init_dest(&res, &exp); + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, 0xcc, 0); + H_HF(res) = INTRINSIC (_mask_cvtx_roundps_ph) (H_HF(res), 0xcc, + SF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _mask_cvtx_roundps_ph); + + EMULATE(cvtxps2_ph)(&exp, src3f, N_ELEMS, 0xf1, 1); + H_HF(res) = INTRINSIC (_maskz_cvtx_roundps_ph) (0xf1, SF(src3f), _ROUND_NINT); + CHECK_RESULT (&res, &exp, CHECK_ELEMS, _maskz_cvtx_roundps_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c new file mode 100644 index 0000000..4e8515e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi64_ph (x1); + res1 = _mm512_mask_cvtepi64_ph (res, m8, x2); + res2 = _mm512_maskz_cvtepi64_ph (m8, x3); + res = _mm512_cvt_roundepi64_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepi64_ph (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundepi64_ph (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c new file mode 100644 index 0000000..cb213b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 64) + +void NOINLINE +EMULATE(cvtq2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u64[i]; + } + } + + // The left part should be zero + for (i = n_el; i < 16; i++) + v5.f32[i] = 0; + + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvtepi64_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, 8, _cvtepi64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvtepi64_ph) (res.xmmh[0], 0xcc, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _mask_cvtepi64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvtepi64_ph) (0xf1, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _maskz_cvtepi64_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvt_roundepi64_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _cvt_roundepi64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvt_roundepi64_ph) (res.xmmh[0], 0xcc, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _mask_cvt_roundepi64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvt_roundepi64_ph) (0xf1, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _maskz_cvt_roundepi64_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c new file mode 100644 index 0000000..b663ca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1; +volatile __m128d x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_cvtsd_sh (x1, x2); + res = _mm_mask_cvtsd_sh (res, m8, x1, x2); + res = _mm_maskz_cvtsd_sh (m8, x1, x2); + res = _mm_cvt_roundsd_sh (x1, x2, 8); + res = _mm_mask_cvt_roundsd_sh (res, m8, x1, x2, 8); + res = _mm_maskz_cvt_roundsd_sh (m8, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c new file mode 100644 index 0000000..5523620 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c @@ -0,0 +1,60 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsd2sh(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = (float)op2.f64[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsd2sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_cvt_roundsd_sh(src1.xmmh[0], src2.xmmd[0], + _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsd_sh"); + + init_dest(&res, &exp); + emulate_vcvtsd2sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_mask_cvt_roundsd_sh(res.xmmh[0], 0x1, src1.xmmh[0], + src2.xmmd[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsd_sh"); + + emulate_vcvtsd2sh(&exp, src1, src2, 0x2, 1); + res.xmmh[0] = _mm_maskz_cvt_roundsd_sh(0x2, src1.xmmh[0], + src2.xmmd[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsd_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c new file mode 100644 index 0000000..59719ed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ + +#include <immintrin.h> + +volatile __m128d res; +volatile __m128d x1; +volatile __m128h x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_cvtsh_sd (x1, x2); + res = _mm_mask_cvtsh_sd (res, m8, x1, x2); + res = _mm_maskz_cvtsh_sd (m8, x1, x2); + res = _mm_cvt_roundsh_sd (x1, x2, 8); + res = _mm_mask_cvt_roundsh_sd (res, m8, x1, x2, 8); + res = _mm_maskz_cvt_roundsh_sd (m8, x1, x2, 4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c new file mode 100644 index 0000000..e6bdc95 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c @@ -0,0 +1,57 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsh2sd(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + + unpack_ph_2twops(op2, &v3, &v4); + + if ((k&1) || !k) + v5.f64[0] = v3.f32[0]; + else if (zero_mask) + v5.f64[0] = 0; + else + v5.f64[0] = dest->f64[0]; + + v5.f64[1] = op1.f64[1]; + + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsh2sd(&exp, src1, src2, 0x1, 0); + res.xmmd[0] = _mm_cvt_roundsh_sd(src1.xmmd[0], src2.xmmh[0], + _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_sd"); + + init_dest(&res, &exp); + emulate_vcvtsh2sd(&exp, src1, src2, 0x1, 0); + res.xmmd[0] = _mm_mask_cvt_roundsh_sd(res.xmmd[0], 0x1, src1.xmmd[0], + src2.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsh_sd"); + + emulate_vcvtsh2sd(&exp, src1, src2, 0x2, 1); + res.xmmd[0] = _mm_maskz_cvt_roundsh_sd(0x2, src1.xmmd[0], + src2.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsh_sd"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c new file mode 100644 index 0000000..f29c953 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + + +#include <immintrin.h> + +volatile __m128h x1; +volatile int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvtsh_i32 (x1); + res1 = _mm_cvt_roundsh_i32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c new file mode 100644 index 0000000..89c492c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.i32[0] = _mm_cvt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_i32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c new file mode 100644 index 0000000..0289ebf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + + +#include <immintrin.h> + +volatile __m128h x1; +volatile long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvtsh_i64 (x1); + res2 = _mm_cvt_roundsh_i64 (x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c new file mode 100644 index 0000000..6a5e836 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c @@ -0,0 +1,52 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.s64[0] = _mm_cvt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_i64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c new file mode 100644 index 0000000..e6c369c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ + +#include <immintrin.h> + +volatile __m128 res; +volatile __m128 x1; +volatile __m128h x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_cvtsh_ss (x1, x2); + res = _mm_mask_cvtsh_ss (res, m8, x1, x2); + res = _mm_maskz_cvtsh_ss (m8, x1, x2); + res = _mm_cvt_roundsh_ss (x1, x2, 8); + res = _mm_mask_cvt_roundsh_ss (res, m8, x1, x2, 8); + res = _mm_maskz_cvt_roundsh_ss (m8, x1, x2, 4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c new file mode 100644 index 0000000..3195983 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c @@ -0,0 +1,59 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + + void NOINLINE +emulate_vcvtsh2ss(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op2, &v3, &v4); + if ((k&1) || !k) + v5.f32[0] = v3.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = dest->f32[0]; + + for (i = 1; i < 4; i++) + v5.f32[i] = op1.f32[i]; + + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsh2ss(&exp, src1, src2, 0x1, 0); + res.xmm[0] = _mm_cvt_roundsh_ss(src1.xmm[0], src2.xmmh[0], + _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_ss"); + + init_dest(&res, &exp); + emulate_vcvtsh2ss(&exp, src1, src2, 0x1, 0); + res.xmm[0] = _mm_mask_cvt_roundsh_ss(res.xmm[0], 0x1, src1.xmm[0], + src2.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsh_ss"); + + emulate_vcvtsh2ss(&exp, src1, src2, 0x2, 1); + res.xmm[0] = _mm_maskz_cvt_roundsh_ss(0x2, src1.xmm[0], + src2.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsh_ss"); + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c new file mode 100644 index 0000000..7d00867 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + + +#include <immintrin.h> + +volatile __m128h x1; +volatile unsigned int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvtsh_u32 (x1); + res1 = _mm_cvt_roundsh_u32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c new file mode 100644 index 0000000..466ce6e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.u32[0] = _mm_cvt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_u32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c new file mode 100644 index 0000000..363252d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2 " } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x1; +volatile unsigned long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvtsh_u64 (x1); + res2 = _mm_cvt_roundsh_u64 (x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c new file mode 100644 index 0000000..74643ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.u64[0] = _mm_cvt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, 4, "_mm_cvt_roundsh_u64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c new file mode 100644 index 0000000..19d1b96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsi2shl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsi2shl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x; +volatile int n; + +void extern +avx512f_test (void) +{ + x = _mm_cvti32_sh (x, n); + x = _mm_cvt_roundi32_sh (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c new file mode 100644 index 0000000..d9c9a85 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundi32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundi64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsi2sh(&exp, src1, 99, 0, 32); + res.xmmh[0] = _mm_cvt_roundi32_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundi32_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c new file mode 100644 index 0000000..7781e36 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsi2shq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsi2shq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x; +volatile long long n; + +void extern +avx512f_test (void) +{ + x = _mm_cvti64_sh (x, n); + x = _mm_cvt_roundi64_sh (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c new file mode 100644 index 0000000..6f66a87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundi32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundi64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsi2sh(&exp, src1, 0, 99, 64); + res.xmmh[0] = _mm_cvt_roundi64_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundi64_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c new file mode 100644 index 0000000..63ad090 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1; +volatile __m128 x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_cvtss_sh (x1, x2); + res = _mm_mask_cvtss_sh (res, m8, x1, x2); + res = _mm_maskz_cvtss_sh (m8, x1, x2); + res = _mm_cvt_roundss_sh (x1, x2, 8); + res = _mm_mask_cvt_roundss_sh (res, m8, x1, x2, 8); + res = _mm_maskz_cvt_roundss_sh (m8, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c new file mode 100644 index 0000000..94981bb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c @@ -0,0 +1,60 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtss2sh(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = op2.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtss2sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_cvt_roundss_sh(src1.xmmh[0], src2.xmm[0], + _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundss_sh"); + + init_dest(&res, &exp); + emulate_vcvtss2sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_mask_cvt_roundss_sh(res.xmmh[0], 0x1, src1.xmmh[0], + src2.xmm[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundss_sh"); + + emulate_vcvtss2sh(&exp, src1, src2, 0x2, 1); + res.xmmh[0] = _mm_maskz_cvt_roundss_sh(0x2, src1.xmmh[0], + src2.xmm[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundss_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c new file mode 100644 index 0000000..0e44aaf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epi32 (x1); + res1 = _mm512_mask_cvttph_epi32 (res, m16, x2); + res2 = _mm512_maskz_cvttph_epi32 (m16, x3); + res = _mm512_cvtt_roundph_epi32 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epi32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epi32 (m16, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c new file mode 100644 index 0000000..c18fefb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epi32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvttph_epi32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epi32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epi32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epi32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi32); +#endif + + if (n_errs != 0) + abort (); +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c new file mode 100644 index 0000000..1241694 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epi64 (x1); + res1 = _mm512_mask_cvttph_epi64 (res, m8, x2); + res2 = _mm512_maskz_cvttph_epi64 (m8, x3); + res = _mm512_cvtt_roundph_epi64 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epi64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epi64 (m8, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c new file mode 100644 index 0000000..2a9a2ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epi64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvttph_epi64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epi64) (0xfa, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epi64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epi64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi64) (0xfa, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c new file mode 100644 index 0000000..0fd60f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epu32 (x1); + res1 = _mm512_mask_cvttph_epu32 (res, m16, x2); + res2 = _mm512_maskz_cvttph_epu32 (m16, x3); + res = _mm512_cvtt_roundph_epu32 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epu32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epu32 (m16, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c new file mode 100644 index 0000000..98bce37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epu32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvttph_epu32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epu32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epu32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epu32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu32); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c new file mode 100644 index 0000000..04fee29 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epu64 (x1); + res1 = _mm512_mask_cvttph_epu64 (res, m8, x2); + res2 = _mm512_maskz_cvttph_epu64 (m8, x3); + res = _mm512_cvtt_roundph_epu64 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epu64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epu64 (m8, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c new file mode 100644 index 0000000..31879ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epu64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvttph_epu64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epu64) (0xfc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epu64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epu64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu64) (0xfc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c new file mode 100644 index 0000000..b31af84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epu16 (x1); + res1 = _mm512_mask_cvttph_epu16 (res, m32, x2); + res2 = _mm512_maskz_cvttph_epu16 (m32, x3); + res = _mm512_cvtt_roundph_epu16 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epu16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epu16 (m32, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c new file mode 100644 index 0000000..34e94e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epu16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvttph_epu16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epu16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epu16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epu16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu16); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c new file mode 100644 index 0000000..a918594 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvttph_epi16 (x1); + res1 = _mm512_mask_cvttph_epi16 (res, m32, x2); + res2 = _mm512_maskz_cvttph_epi16 (m32, x3); + res = _mm512_cvtt_roundph_epi16 (x1, 4); + res1 = _mm512_mask_cvtt_roundph_epi16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvtt_roundph_epi16 (m32, x3, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c new file mode 100644 index 0000000..23bc8e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c @@ -0,0 +1,83 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res, exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvttph_epi16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvttph_epi16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvttph_epi16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtt_roundph_epi16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtt_roundph_epi16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi16); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1a.c new file mode 100644 index 0000000..80d84fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsh2si\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x1; +volatile int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvttsh_i32 (x1); + res1 = _mm_cvtt_roundsh_i32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1b.c new file mode 100644 index 0000000..c5b0a64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.i32[0] = _mm_cvtt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvtt_roundsh_i32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1a.c new file mode 100644 index 0000000..76a9053 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsh2si\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x1; +volatile long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvttsh_i64 (x1); + res2 = _mm_cvtt_roundsh_i64 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1b.c new file mode 100644 index 0000000..4e0fe5b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2si64-1b.c @@ -0,0 +1,52 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.s64[0] = _mm_cvtt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvtt_roundsh_i64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1a.c new file mode 100644 index 0000000..5956457 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvttsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsh2usi\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x1; +volatile unsigned int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvttsh_u32 (x1); + res1 = _mm_cvtt_roundsh_u32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1b.c new file mode 100644 index 0000000..214e3e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.u32[0] = _mm_cvtt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvtt_roundsh_u32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1a.c new file mode 100644 index 0000000..23e8e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2 " } */ +/* { dg-final { scan-assembler-times "vcvttsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsh2usi\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x1; +volatile unsigned long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvttsh_u64 (x1); + res2 = _mm_cvtt_roundsh_u64 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1b.c new file mode 100644 index 0000000..863fb6e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttsh2usi64-1b.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.u64[0] = _mm_cvtt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, 4, "_mm_cvtt_roundsh_u64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c new file mode 100644 index 0000000..8d90ef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu32_ph (x1); + res1 = _mm512_mask_cvtepu32_ph (res, m16, x2); + res2 = _mm512_maskz_cvtepu32_ph (m16, x3); + res = _mm512_cvt_roundepu32_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepu32_ph (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundepu32_ph (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c new file mode 100644 index 0000000..e9c1cd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) + +void NOINLINE +EMULATE(cvtd2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u32[i]; + } + } + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res)= INTRINSIC (_cvtepu32_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepu32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvtepu32_ph) (H_HF(res), HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepu32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvtepu32_ph) (HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepu32_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res)= INTRINSIC (_cvt_roundepu32_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepu32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvt_roundepu32_ph) (H_HF(res), HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepu32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvt_roundepu32_ph) (HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepu32_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c new file mode 100644 index 0000000..a234bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu64_ph (x1); + res1 = _mm512_mask_cvtepu64_ph (res, m8, x2); + res2 = _mm512_maskz_cvtepu64_ph (m8, x3); + res = _mm512_cvt_roundepu64_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepu64_ph (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundepu64_ph (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c new file mode 100644 index 0000000..873d910 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c @@ -0,0 +1,83 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 64) + +void NOINLINE +EMULATE(cvtq2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u64[i]; + } + } + + // The left part should be zero + for (i = n_el; i < 16; i++) + v5.f32[i] = 0; + + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvtepu64_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, 8, _cvtepu64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvtepu64_ph) (res.xmmh[0], 0xcc, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _mask_cvtepu64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xc1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvtepu64_ph) (0xc1, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _maskz_cvtepu64_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvt_roundepu64_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _cvt_roundepu64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvt_roundepu64_ph) (res.xmmh[0], 0xcc, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _mask_cvt_roundepu64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xc1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvt_roundepu64_ph) (0xc1, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _maskz_cvt_roundepu64_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c new file mode 100644 index 0000000..3b6d095 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtusi2shl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2shl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x; +volatile unsigned n; + +void extern +avx512f_test (void) +{ + x = _mm_cvtu32_sh (x, n); + x = _mm_cvt_roundu32_sh (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c new file mode 100644 index 0000000..d339f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtusi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundu32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundu64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtusi2sh(&exp, src1, 99, 0, 32); + res.xmmh[0] = _mm_cvt_roundu32_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundu32_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c new file mode 100644 index 0000000..30fcdc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtusi2shq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2shq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x; +volatile unsigned long long n; + +void extern +avx512f_test (void) +{ + x = _mm_cvtu64_sh (x, n); + x = _mm_cvt_roundu64_sh (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c new file mode 100644 index 0000000..20e711e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtusi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundu32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundu64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtusi2sh(&exp, src1, 0, 99, 64); + res.xmmh[0] = _mm_cvt_roundu64_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundu64_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c new file mode 100644 index 0000000..43c96a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res; +volatile __m512i x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu16_ph (x1); + res = _mm512_mask_cvtepu16_ph (res, m32, x1); + res = _mm512_maskz_cvtepu16_ph (m32, x1); + res = _mm512_cvt_roundepu16_ph (x1, 4); + res = _mm512_mask_cvt_roundepu16_ph (res, m32, x1, 8); + res = _mm512_maskz_cvt_roundepu16_ph (m32, x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c new file mode 100644 index 0000000..6d6b6da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c @@ -0,0 +1,93 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtw2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.f32[i] = v7.f32[i]; + } + } + else { + v5.f32[i] = op1.u16[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.f32[i] = v8.f32[i]; + } + } + else { + v6.f32[i] = op1.u16[i+16]; + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvtepu16_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepu16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvtepu16_ph) (HF(res), MASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepu16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvtepu16_ph) (ZMASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepu16_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvt_roundepu16_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepu16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvt_roundepu16_ph) (HF(res), MASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepu16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvt_roundepu16_ph) (ZMASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepu16_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c new file mode 100644 index 0000000..c6eaee1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res; +volatile __m512i x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi16_ph (x1); + res = _mm512_mask_cvtepi16_ph (res, m32, x1); + res = _mm512_maskz_cvtepi16_ph (m32, x1); + res = _mm512_cvt_roundepi16_ph (x1, 4); + res = _mm512_mask_cvt_roundepi16_ph (res, m32, x1, 8); + res = _mm512_maskz_cvt_roundepi16_ph (m32, x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c new file mode 100644 index 0000000..e02b6fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c @@ -0,0 +1,92 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtw2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.f32[i] = v7.f32[i]; + } + } + else { + v5.f32[i] = op1.u16[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.f32[i] = v8.f32[i]; + } + } + else { + v6.f32[i] = op1.u16[i+16]; + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvtepi16_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepi16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvtepi16_ph) (HF(res), MASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepi16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvtepi16_ph) (ZMASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepi16_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvt_roundepi16_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepi16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvt_roundepi16_ph) (HF(res), MASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepi16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvt_roundepi16_ph) (ZMASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepi16_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1a.c new file mode 100644 index 0000000..a97dddf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfpclassphz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassphz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h x512; +volatile __mmask16 m32; + +void extern +avx512dq_test (void) +{ + m32 = _mm512_fpclass_ph_mask (x512, 13); + m32 = _mm512_mask_fpclass_ph_mask (2, x512, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1b.c new file mode 100644 index 0000000..9ffb560 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1b.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512fp16" } */ +/* { dg-require-effective-target avx512fp16 } */ + +#define AVX512FP16 +#include "avx512f-helper.h" + +#include <math.h> +#include <limits.h> +#include <float.h> +#include "avx512f-mask-type.h" +#define SIZE (AVX512F_LEN / 16) + +#ifndef __FPCLASSPH__ +#define __FPCLASSPH__ +int check_fp_class_hp (_Float16 src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +MASK_TYPE +CALC (_Float16 *s1, int imm) +{ + int i; + MASK_TYPE res = 0; + + for (i = 0; i < SIZE; i++) + if (check_fp_class_hp(s1[i], imm)) + res = res | (1 << i); + + return res; +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, h) src; + MASK_TYPE res1, res2, res_ref = 0; + MASK_TYPE mask = MASK_VALUE; + + src.a[0] = NAN; + src.a[1] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = INTRINSIC (_fpclass_ph_mask) (src.x, 0xFF); + res2 = INTRINSIC (_mask_fpclass_ph_mask) (mask, src.x, 0xFF); + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((mask & res_ref) != res2) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1a.c new file mode 100644 index 0000000..7a31fd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vfpclasssh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclasssh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x128; +volatile __mmask8 m8; + +void extern +avx512dq_test (void) +{ + m8 = _mm_fpclass_sh_mask (x128, 13); + m8 = _mm_mask_fpclass_sh_mask (m8, x128, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1b.c new file mode 100644 index 0000000..bdc6f9f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclasssh-1b.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512fp16" } */ +/* { dg-require-effective-target avx512fp16 } */ + +#define AVX512FP16 +#include "avx512f-helper.h" + +#include <math.h> +#include <limits.h> +#include <float.h> +#include "avx512f-mask-type.h" +#define SIZE (128 / 16) + +#ifndef __FPCLASSSH__ +#define __FPCLASSSH__ +int check_fp_class_hp (_Float16 src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +__mmask8 +CALC (_Float16 *s1, int imm) +{ + int i; + __mmask8 res = 0; + + if (check_fp_class_hp(s1[0], imm)) + res = res | 1; + + return res; +} + +void +TEST (void) +{ + int i; + union128h src; + __mmask8 res1, res2, res_ref = 0; + __mmask8 mask = MASK_VALUE; + + src.a[0] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = _mm_fpclass_sh_mask (src.x, 0xFF); + res2 = _mm_mask_fpclass_sh_mask (mask, src.x, 0xFF); + + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((mask & res_ref) != res2) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1a.c new file mode 100644 index 0000000..993cbd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1} } */ + +#include <immintrin.h> + +volatile __m512h x; +volatile __mmask32 m; + +void extern +avx512f_test (void) +{ + x = _mm512_getexp_ph (x); + x = _mm512_mask_getexp_ph (x, m, x); + x = _mm512_maskz_getexp_ph (m, x); + x = _mm512_getexp_round_ph (x, _MM_FROUND_NO_EXC); + x = _mm512_mask_getexp_round_ph (x, m, x, _MM_FROUND_NO_EXC); + x = _mm512_maskz_getexp_round_ph (m, x, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1b.c new file mode 100644 index 0000000..3483c95 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpph-1b.c @@ -0,0 +1,99 @@ + /* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(getexp_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + float emu[32]; + __mmask16 m1, m2; + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + v3.zmm = _mm512_getexp_round_ps(v1.zmm, _ROUND_CUR); + v4.zmm = _mm512_getexp_round_ps(v2.zmm, _ROUND_CUR); + for (i=0; i<16; i++) + { + emu[i] = v3.f32[i]; + emu[i+16] = v4.f32[i]; + } + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = emu[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = emu[i+16]; + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(getexp_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_getexp_ph) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _getexp_ph); + + init_dest(&res, &exp); + EMULATE(getexp_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_getexp_ph) (HF(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_getexp_ph); + + EMULATE(getexp_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_getexp_ph) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_getexp_ph); +#if AVX512F_LEN == 512 + EMULATE(getexp_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_getexp_round_ph) (HF(src1), _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _getexp_round_ph); + + init_dest(&res, &exp); + EMULATE(getexp_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_getexp_round_ph) (HF(res), MASK_VALUE, HF(src1), + _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_getexp_round_ph); + + EMULATE(getexp_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_getexp_round_ph) (ZMASK_VALUE, HF(src1), _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_getexp_round_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1a.c new file mode 100644 index 0000000..397fd3e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\{\n\]\[^\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\{\n\]\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\{\n\]\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\, %xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetexpsh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x; +volatile __mmask8 m; + +void extern +avx512f_test (void) +{ + x = _mm_getexp_sh (x, x); + x = _mm_mask_getexp_sh (x, m, x, x); + x = _mm_maskz_getexp_sh (m, x, x); + x = _mm_getexp_round_sh (x, x, _MM_FROUND_NO_EXC); + x = _mm_mask_getexp_round_sh (x, m, x, x, _MM_FROUND_NO_EXC); + x = _mm_maskz_getexp_round_sh (m, x, x, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1b.c new file mode 100644 index 0000000..ca9834d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetexpsh-1b.c @@ -0,0 +1,61 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_getexp_sh(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v0, v1, v2, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + v0.xmm[0] = _mm_getexp_round_ss (v1.xmm[0], v1.xmm[0], _ROUND_CUR); + + if ((k&1) || !k) + v5.f32[0] = v0.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_getexp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_getexp_round_sh(exp.xmmh[0], src1.xmmh[0], _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_getexp_round_sh"); + + init_dest(&res, &exp); + emulate_getexp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_getexp_round_sh(res.xmmh[0], 0x1, exp.xmmh[0], + src1.xmmh[0], _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_mask_getexp_round_sh"); + + emulate_getexp_sh(&exp, src1, 0x3, 1); + res.xmmh[0] = _mm_maskz_getexp_round_sh(0x3, exp.xmmh[0], src1.xmmh[0], + _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_getexp_round_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1a.c new file mode 100644 index 0000000..69e0c72 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16" } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h x, y; +volatile __mmask32 m; + +void extern +avx512f_test (void) +{ + x = _mm512_getmant_ph (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm512_mask_getmant_ph (x, m, y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm512_maskz_getmant_ph (m, y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm512_getmant_round_ph (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm512_mask_getmant_round_ph (x, m, y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm512_maskz_getmant_round_ph (m, y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1b.c new file mode 100644 index 0000000..c18d1aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantph-1b.c @@ -0,0 +1,102 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(getmant_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + float emu[32]; + __mmask16 m1, m2; + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + v3.zmm = _mm512_getmant_round_ps(v1.zmm, 2, 0, _ROUND_CUR); + v4.zmm = _mm512_getmant_round_ps(v2.zmm, 2, 0, _ROUND_CUR); + for (i=0; i<16; i++) + { + emu[i] = v3.f32[i]; + emu[i+16] = v4.f32[i]; + } + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = emu[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = emu[i+16]; + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(getmant_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_getmant_ph) (HF(src1), 2, 0); + CHECK_RESULT (&res, &exp, N_ELEMS, _getmant_ph); + + init_dest(&res, &exp); + EMULATE(getmant_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_getmant_ph) (HF(res), MASK_VALUE, + HF(src1), 2, 0); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_getmant_ph); + + EMULATE(getmant_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_getmant_ph) (ZMASK_VALUE, HF(src1), + 2, 0); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_getmant_ph); +#if AVX512F_LEN == 512 + EMULATE(getmant_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_getmant_round_ph) (HF(src1), 2, 0, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _getmant_round_ph); + + init_dest(&res, &exp); + EMULATE(getmant_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_getmant_round_ph) (HF(res), MASK_VALUE, + HF(src1), 2, 0, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_getmant_round_ph); + + EMULATE(getmant_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_getmant_round_ph) (ZMASK_VALUE, HF(src1), + 2, 0, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_getmant_round_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1a.c new file mode 100644 index 0000000..b533f20 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16" } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantsh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h x, y, z; +volatile __mmask8 m; + +void extern +avx512f_test (void) +{ + x = _mm_getmant_sh (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_mask_getmant_sh (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_maskz_getmant_sh (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm_getmant_round_sh (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm_mask_getmant_round_sh (x, m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); + x = _mm_maskz_getmant_round_sh (m, y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1b.c new file mode 100644 index 0000000..bee8b04 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vgetmantsh-1b.c @@ -0,0 +1,62 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_getmant_sh(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v0, v1, v2, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + v0.xmm[0] = _mm_getmant_round_ss (v1.xmm[0], v1.xmm[0], 2, 0, _ROUND_CUR); + + if ((k&1) || !k) + v5.f32[0] = v0.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_getmant_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_getmant_round_sh(src1.xmmh[0], exp.xmmh[0], + 2, 0, _ROUND_CUR); + check_results(&res, &exp, 1, "_mm_getmant_round_sh"); + + init_dest(&res, &exp); + emulate_getmant_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_getmant_round_sh(res.xmmh[0], 0x1, src1.xmmh[0], + exp.xmmh[0], 2, 0, _ROUND_CUR); + check_results(&res, &exp, 1, "_mm_mask_getmant_round_sh"); + + emulate_getmant_sh(&exp, src1, 0x3, 1); + res.xmmh[0] = _mm_maskz_getmant_round_sh(0x3, src1.xmmh[0], exp.xmmh[0], + 2, 0, _ROUND_CUR); + check_results(&res, &exp, 1, "_mm_maskz_getmant_round_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1a.c new file mode 100644 index 0000000..e35be10 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1a.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+%xmm\[0-9\]+\[^\n\r\]*%\[er\]ax+\[^\n\r]*\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+\[^\n\r\]*%\[er\]ax+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+\[^\n\r\]*%\[er\]ax+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^z\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vmovsh\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +extern _Float16 const* p; +volatile __m128h x1, x2, res; +volatile __mmask8 m8; + +void +avx512f_test (void) +{ + x2 = _mm_mask_load_sh (x1, m8, p); + x2 = _mm_maskz_load_sh (m8, p); + _mm_mask_store_sh (p, m8, x1); + + res = _mm_move_sh (x1, x2); + res = _mm_mask_move_sh (res, m8, x1, x2); + res = _mm_maskz_move_sh (m8, x1, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1b.c new file mode 100644 index 0000000..cea224a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovsh-1b.c @@ -0,0 +1,115 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +void NOINLINE +emulate_mov2_load_sh(V512 * dest, V512 op1, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = v1.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; //remains unchanged + + for (i = 1; i < 8; i++) + v5.f32[i] = 0; + + *dest = pack_twops_2ph(v5, v6); +} + +void NOINLINE +emulate_mov3_load_sh(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = v3.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; //remains unchanged + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void NOINLINE +emulate_mov2_store_sh(V512 * dest, V512 op1, __mmask8 k) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = v1.f32[0]; + else + v5.f32[0] = v7.f32[0]; //remains unchanged + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + // no mask + emulate_mov2_load_sh (&exp, src1, 0x0, 0); + res.xmmh[0] = _mm_load_sh((const void *)&(src1.u16[0])); + check_results(&res, &exp, 8, "_mm_load_sh"); + + // with mask and mask bit is set + emulate_mov2_load_sh (&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_load_sh(res.xmmh[0], 0x1, (const void *)&(src1.u16[0])); + check_results(&res, &exp, 8, "_mm__mask_load_sh"); + + // with zero-mask + emulate_mov2_load_sh (&exp, src1, 0x0, 1); + res.xmmh[0] = _mm_maskz_load_sh(0x1, (const void *)&(src1.u16[0])); + check_results(&res, &exp, 8, "_mm_maskz_load_sh"); + + emulate_mov3_load_sh (&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_mask_move_sh(res.xmmh[0], 0x1, src1.xmmh[0], src2.xmmh[0]); + check_results(&res, &exp, 8, "_mm_mask_move_sh"); + + emulate_mov3_load_sh (&exp, src1, src2, 0x1, 1); + res.xmmh[0] = _mm_maskz_move_sh(0x1, src1.xmmh[0], src2.xmmh[0]); + check_results(&res, &exp, 8, "_mm_maskz_move_sh"); + + // no mask + emulate_mov2_store_sh (&exp, src1, 0x0); + _mm_store_sh((void *)&(res.u16[0]), src1.xmmh[0]); + check_results(&exp, &res, 1, "_mm_store_sh"); + + // with mask + emulate_mov2_store_sh (&exp, src1, 0x1); + _mm_mask_store_sh((void *)&(res.u16[0]), 0x1, src1.xmmh[0]); + check_results(&exp, &res, 1, "_mm_mask_store_sh"); + + if (n_errs != 0) { + abort (); + } +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1a.c new file mode 100644 index 0000000..177802c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1a.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vmovw\[^-]" 1 } } */ +/* { dg-final { scan-assembler-times "vpextrw" 1 } } */ +#include <immintrin.h> + +volatile __m128i x1; +volatile short x2; + +void extern +avx512f_test (void) +{ + x1 = _mm_cvtsi16_si128 (x2); + x2 = _mm_cvtsi128_si16 (x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c new file mode 100644 index 0000000..a96007d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-1b.c @@ -0,0 +1,27 @@ +/* { dg-do run {target avx512fp16} } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" + +static void +do_test (void) +{ + union128i_w u; + short b = 128; + short e[8] = {0,0,0,0,0,0,0,0}; + + u.x = _mm_cvtsi16_si128 (b); + + e[0] = b; + + if (check_union128i_w (u, e)) + abort (); + u.a[0] = 123; + b = _mm_cvtsi128_si16 (u.x); + if (u.a[0] != b) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2a.c new file mode 100644 index 0000000..efa24e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2a.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +__m128i +__attribute__ ((noinline, noclone)) +foo1 (short x) +{ + return __extension__ (__m128i)(__v8hi) { x, 0, 0, 0, 0, 0, 0, 0 }; +} + +__m128i +__attribute__ ((noinline, noclone)) +foo2 (short *x) +{ + return __extension__ (__m128i)(__v8hi) { *x, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* { dg-final { scan-assembler-times "vmovw\[^-\n\r]*xmm0" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2b.c new file mode 100644 index 0000000..b680a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-2b.c @@ -0,0 +1,53 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +#include <string.h> + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" +#include "avx512fp16-vmovw-2a.c" + +__m128i +__attribute__ ((noinline,noclone)) +foo3 (__m128i x) +{ + return foo1 (((__v8hi) x)[0]); +} + +static void +do_test (void) +{ + short x; + union128i_w u = { -1, -1,}; + union128i_w exp = { 0, 0}; + __m128i v; + union128i_w a; + + x = 25; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo1 (x); + a.x = v; + if (check_union128i_w (a, exp.a)) + abort (); + + x = 33; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo2 (&x); + a.x = v; + if (check_union128i_w (a, exp.a)) + abort (); + + x = -33; + u.a[0] = x; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo3 (u.x); + a.x = v; + if (check_union128i_w (a, exp.a)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3a.c new file mode 100644 index 0000000..c603107 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3a.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +typedef short __v16hi __attribute__ ((__vector_size__ (32))); +typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); + +__m256i +__attribute__ ((noinline, noclone)) +foo1 (short x) +{ + return __extension__ (__m256i)(__v16hi) { x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +__m256i +__attribute__ ((noinline, noclone)) +foo2 (short *x) +{ + return __extension__ (__m256i)(__v16hi) { *x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* { dg-final { scan-assembler-times "vmovw\[^-\n\r]*xmm0" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3b.c new file mode 100644 index 0000000..13c1f65 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-3b.c @@ -0,0 +1,52 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +#include <string.h> + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" +#include "avx512fp16-vmovw-3a.c" + +__m256i +__attribute__ ((noinline,noclone)) +foo3 (__m256i x) +{ + return foo1 (((__v16hi) x)[0]); +} + +static void +do_test (void) +{ + short x; + union256i_w u = { -1, -1, -1, -1 }; + union256i_w exp = { 0, 0, 0, 0 }; + + __m256i v; + union256i_w a; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo1 (x); + a.x = v; + if (check_union256i_w (a, exp.a)) + abort (); + + x = 33; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo2 (&x); + a.x = v; + if (check_union256i_w (a, exp.a)) + abort (); + + x = -23; + u.a[0] = x; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo3 (u.x); + a.x = v; + if (check_union256i_w (a, exp.a)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4a.c new file mode 100644 index 0000000..2ba198d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +typedef short __v32hi __attribute__ ((__vector_size__ (64))); +typedef long long __m512i __attribute__ ((__vector_size__ (64), __may_alias__)); + +__m512i +__attribute__ ((noinline, noclone)) +foo1 (short x) +{ + return __extension__ (__m512i)(__v32hi) { x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +__m512i +__attribute__ ((noinline, noclone)) +foo2 (short *x) +{ + return __extension__ (__m512i)(__v32hi) { *x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* { dg-final { scan-assembler-times "vmovw\[^-\n\r]*xmm0" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4b.c new file mode 100644 index 0000000..ec6477b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vmovw-4b.c @@ -0,0 +1,52 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16" } */ + +#include <string.h> + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512-check.h" +#include "avx512fp16-vmovw-4a.c" + +__m512i +__attribute__ ((noinline,noclone)) +foo3 (__m512i x) +{ + return foo1 (((__v32hi) x)[0]); +} + +static void +do_test (void) +{ + short x = 25; + union512i_w u = { -1, -1, -1, -1, -1, -1, -1, -1 }; + union512i_w exp = { 0, 0, 0, 0, 0, 0, 0, 0 }; + + __m512i v; + union512i_w a; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo1 (x); + a.x = v; + if (check_union512i_w (a, exp.a)) + abort (); + + x = 55; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo2 (&x); + a.x = v; + if (check_union512i_w (a, exp.a)) + abort (); + + x = 33; + u.a[0] = x; + exp.a[0] = x; + memset (&v, -1, sizeof (v)); + v = foo3 (u.x); + a.x = v; + if (check_union512i_w (a, exp.a)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c new file mode 100644 index 0000000..6a5c642 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res; +volatile __m512h x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_rcp_ph (x1); + res = _mm512_mask_rcp_ph (res, m32, x1); + res = _mm512_maskz_rcp_ph (m32, x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c new file mode 100644 index 0000000..4a65451 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(rcp_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = 1. / v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = 1. / v2.f32[i]; + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(rcp_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_rcp_ph) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _rcp_ph); + + init_dest(&res, &exp); + EMULATE(rcp_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_rcp_ph) (HF(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_rcp_ph); + + EMULATE(rcp_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_rcp_ph) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_rcp_ph); + + if (n_errs != 0) + abort (); +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c new file mode 100644 index 0000000..0a5a18e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_rcp_sh (x1, x2); + res = _mm_mask_rcp_sh (res, m8, x1, x2); + res = _mm_maskz_rcp_sh (m8, x1, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c new file mode 100644 index 0000000..5316895 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c @@ -0,0 +1,57 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_rcp_sh(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = 1. / v1.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_rcp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_rcp_sh(exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_rcp_sh"); + + init_dest(&res, &exp); + emulate_rcp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_rcp_sh(res.xmmh[0], 0x1, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_mask_rcp_sh"); + + emulate_rcp_sh(&exp, src1, 0x3, 1); + res.xmmh[0] = _mm_maskz_rcp_sh(0x3, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_rcp_sh"); + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c new file mode 100644 index 0000000..536c1ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +#define IMM 123 + +volatile __m512h x1; +volatile __mmask32 m; + +void extern +avx512fp16_test (void) +{ + x1 = _mm512_reduce_ph (x1, IMM); + x1 = _mm512_mask_reduce_ph (x1, m, x1, IMM); + x1 = _mm512_maskz_reduce_ph (m, x1, IMM); + x1 = _mm512_reduce_round_ph (x1, IMM, 8); + x1 = _mm512_mask_reduce_round_ph (x1, m, x1, IMM, 8); + x1 = _mm512_maskz_reduce_round_ph (m, x1, IMM, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c new file mode 100644 index 0000000..20d1ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c @@ -0,0 +1,116 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +#ifndef __REDUCEPH__ +#define __REDUCEPH__ +V512 borrow_reduce_ps(V512 v, int imm8) +{ + V512 temp; + switch (imm8) + { + case 1: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 1);break; + case 2: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 2);break; + case 3: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 3);break; + case 4: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 4);break; + case 5: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 5);break; + case 6: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 6);break; + case 7: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 7);break; + case 8: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 8);break; + } + return temp; +} +#endif + +void NOINLINE +EMULATE(reduce_ph) (V512 * dest, V512 op1, + __mmask32 k, int imm8, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + V512 t1,t2; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + t1 = borrow_reduce_ps(v1, imm8); + t2 = borrow_reduce_ps(v2, imm8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = t1.f32[i]; + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = t2.f32[i]; + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(reduce_ph) (&exp, src1, NET_MASK, 6, 0); + HF(res) = INTRINSIC (_reduce_ph) (HF(src1), 6); + CHECK_RESULT (&res, &exp, N_ELEMS, _reduce_ph); + + init_dest(&res, &exp); + EMULATE(reduce_ph) (&exp, src1, MASK_VALUE, 5, 0); + HF(res) = INTRINSIC (_mask_reduce_ph) (HF(res), MASK_VALUE, HF(src1), 5); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_reduce_ph); + + EMULATE(reduce_ph) (&exp, src1, ZMASK_VALUE, 4, 1); + HF(res) = INTRINSIC (_maskz_reduce_ph) (ZMASK_VALUE, HF(src1), 4); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_reduce_ph); + +#if AVX512F_LEN == 512 + EMULATE(reduce_ph) (&exp, src1, NET_MASK, 6, 0); + HF(res) = INTRINSIC (_reduce_round_ph) (HF(src1), 6, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _reduce_round_ph); + + init_dest(&res, &exp); + EMULATE(reduce_ph) (&exp, src1, MASK_VALUE, 5, 0); + HF(res) = INTRINSIC (_mask_reduce_round_ph) (HF(res), MASK_VALUE, HF(src1), 5, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_reduce_round_ph); + + EMULATE(reduce_ph) (&exp, src1, ZMASK_VALUE, 4, 1); + HF(res) = INTRINSIC (_maskz_reduce_round_ph) (ZMASK_VALUE, HF(src1), 4, _ROUND_CUR); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_reduce_round_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c new file mode 100644 index 0000000..8036991 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + + +#include <immintrin.h> + +#define IMM 123 + +volatile __m128h x1, x2; +volatile __mmask8 m; + +void extern +avx512fp16_test (void) +{ + x1 = _mm_reduce_sh (x1, x2, IMM); + x1 = _mm_mask_reduce_sh(x1, m, x1, x2, IMM); + x1 = _mm_maskz_reduce_sh(m, x1, x2, IMM); + x1 = _mm_reduce_round_sh (x1, x2, IMM, 4); + x1 = _mm_mask_reduce_round_sh(x1, m, x1, x2, IMM, 8); + x1 = _mm_maskz_reduce_round_sh(m, x1, x2, IMM, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c new file mode 100644 index 0000000..4c5dfe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +V512 borrow_reduce_ps(V512 v, int imm8) +{ + V512 temp; + switch (imm8) + { + case 1: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 1);break; + case 2: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 2);break; + case 3: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 3);break; + case 4: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 4);break; + case 5: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 5);break; + case 6: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 6);break; + case 7: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 7);break; + case 8: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 8);break; + } + return temp; +} + +void NOINLINE +emulate_reduce_sh(V512 * dest, V512 op1, + __mmask32 k, int imm8, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + V512 t1; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + t1 = borrow_reduce_ps(v1, imm8); + + if ((k&1) || !k) + v5.f32[0] = t1.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_reduce_sh(&exp, src1, 0x1, 8, 0); + res.xmmh[0] = _mm_reduce_round_sh(src1.xmmh[0], exp.xmmh[0], 8, _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_reduce_round_sh"); + + init_dest(&res, &exp); + emulate_reduce_sh(&exp, src1, 0x1, 7, 0); + res.xmmh[0] = _mm_mask_reduce_round_sh(res.xmmh[0], 0x1, src1.xmmh[0], exp.xmmh[0], 7, _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_mask_reduce_round_sh"); + + emulate_reduce_sh(&exp, src1, 0x3, 6, 1); + res.xmmh[0] = _mm_maskz_reduce_round_sh(0x3, src1.xmmh[0], exp.xmmh[0], 6, _ROUND_CUR); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_reduce_round_sh"); + + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c new file mode 100644 index 0000000..8a30727 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +#define IMM 123 + +volatile __m512h x1; +volatile __mmask32 m; + +void extern +avx512fp16_test (void) +{ + x1 = _mm512_roundscale_ph (x1, IMM); + x1 = _mm512_mask_roundscale_ph (x1, m, x1, IMM); + x1 = _mm512_maskz_roundscale_ph (m, x1, IMM); + x1 = _mm512_roundscale_round_ph (x1, IMM, 8); + x1 = _mm512_mask_roundscale_round_ph (x1, m, x1, IMM, 8); + x1 = _mm512_maskz_roundscale_round_ph (m, x1, IMM, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c new file mode 100644 index 0000000..d50e755 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c @@ -0,0 +1,101 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(roundscale_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask, int round) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + V512 t1, t2; + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + if (round==0) + { + t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x11); + t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x11); + } + else + { + t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x14); + t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x14); + } + for (i = 0; i < 16; i++) + { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = t1.f32[i]; + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = t2.f32[i]; + } + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res, exp; + + init_src(); + + EMULATE(roundscale_ph) (&exp, src1, NET_MASK, 0, 1); + HF(res) = INTRINSIC (_roundscale_ph) (HF(src1), 0x13); + CHECK_RESULT (&res, &exp, N_ELEMS, _roundscale_ph); + + init_dest(&res, &exp); + EMULATE(roundscale_ph) (&exp, src1, MASK_VALUE, 0, 1); + HF(res) = INTRINSIC (_mask_roundscale_ph) (HF(res), MASK_VALUE, HF(src1), 0x14); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_roundscale_ph); + + EMULATE(roundscale_ph) (&exp, src1, ZMASK_VALUE, 1, 1); + HF(res) = INTRINSIC (_maskz_roundscale_ph) (ZMASK_VALUE, HF(src1), 0x14); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_roundscale_ph); + +#if AVX512F_LEN == 512 + EMULATE(roundscale_ph) (&exp, src1, NET_MASK, 0, 1); + HF(res) = INTRINSIC (_roundscale_round_ph) (HF(src1), 0x13, 0x08); + CHECK_RESULT (&res, &exp, N_ELEMS, _roundscale_round_ph); + + init_dest(&res, &exp); + EMULATE(roundscale_ph) (&exp, src1, MASK_VALUE, 0, 1); + HF(res) = INTRINSIC (_mask_roundscale_round_ph) (HF(res), MASK_VALUE, HF(src1), 0x14, 0x08); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_roundscale_round_ph); + + EMULATE(roundscale_ph) (&exp, src1, ZMASK_VALUE, 1, 1); + HF(res) = INTRINSIC (_maskz_roundscale_round_ph) (ZMASK_VALUE, HF(src1), 0x14, 0x08); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_roundscale_round_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c new file mode 100644 index 0000000..bd41b63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +#define IMM 123 + +volatile __m128h x1, x2; +volatile __mmask8 m; + +void extern +avx512fp16_test (void) +{ + x1 = _mm_roundscale_sh (x1, x2, IMM); + x1 = _mm_mask_roundscale_sh(x1, m, x1, x2, IMM); + x1 = _mm_maskz_roundscale_sh(m, x1, x2, IMM); + x1 = _mm_roundscale_round_sh (x1, x2, IMM, 4); + x1 = _mm_mask_roundscale_round_sh(x1, m, x1, x2, IMM, 8); + x1 = _mm_maskz_roundscale_round_sh(m, x1, x2, IMM, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c new file mode 100644 index 0000000..c103389 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c @@ -0,0 +1,62 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_roundscale_sh(V512 * dest, V512 op1, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + V512 t1,t2; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x14); + t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x14); + + if ((k&1) || !k) + v5.f32[0] = t1.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_roundscale_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_roundscale_round_sh(src1.xmmh[0], src1.xmmh[0], 0x1, 0x08); + check_results(&res, &exp, N_ELEMS, "_mm_roundscale_round_sh"); + + init_dest(&res, &exp); + emulate_roundscale_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_roundscale_round_sh(res.xmmh[0], + 0x1, src1.xmmh[0], src1.xmmh[0], 0x1, 0x08); + check_results(&res, &exp, N_ELEMS, "_mm_mask_roundscale_round_sh"); + + emulate_roundscale_sh(&exp, src1, 0x3, 1); + res.xmmh[0] = _mm_maskz_roundscale_round_sh(0x3, src1.xmmh[0], src1.xmmh[0], 0x1, 0x08); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_roundscale_round_sh"); + + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1a.c new file mode 100644 index 0000000..c9671e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1a.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res; +volatile __m512h x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_rsqrt_ph (x1); + res = _mm512_mask_rsqrt_ph (res, m32, x1); + res = _mm512_maskz_rsqrt_ph (m32, x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1b.c new file mode 100644 index 0000000..237971d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtph-1b.c @@ -0,0 +1,77 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(rsqrt_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = 1. / sqrtf(v1.f32[i]); + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = 1. / sqrtf(v2.f32[i]); + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(rsqrt_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_rsqrt_ph) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _rsqrt_ph); + + init_dest(&res, &exp); + EMULATE(rsqrt_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_rsqrt_ph) (HF(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_rsqrt_ph); + + EMULATE(rsqrt_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_rsqrt_ph) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_rsqrt_ph); + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1a.c new file mode 100644 index 0000000..060ce33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1a.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_rsqrt_sh (x1, x2); + res = _mm_mask_rsqrt_sh (res, m8, x1, x2); + res = _mm_maskz_rsqrt_sh (m8, x1, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1b.c new file mode 100644 index 0000000..5f20de7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrsqrtsh-1b.c @@ -0,0 +1,59 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_rsqrt_sh(V512 * dest, V512 op1, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = 1.0 / sqrtf(v1.f32[0]); + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_rsqrt_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_rsqrt_sh(exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_rsqrt_sh"); + + init_dest(&res, &exp); + emulate_rsqrt_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_rsqrt_sh(res.xmmh[0], 0x1, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_mask_rsqrt_sh"); + + emulate_rsqrt_sh(&exp, src1, 0x1, 1); + res.xmmh[0] = _mm_maskz_rsqrt_sh(0x1, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_rsqrt_sh"); + + if (n_errs != 0) { + abort (); + } + +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c new file mode 100644 index 0000000..f3d2789 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_scalef_ph (x1, x2); + res1 = _mm512_mask_scalef_ph (res1, m32, x1, x2); + res2 = _mm512_maskz_scalef_ph (m32, x1, x2); + res = _mm512_scalef_round_ph (x1, x2, 8); + res1 = _mm512_mask_scalef_round_ph (res1, m32, x1, x2, 8); + res2 = _mm512_maskz_scalef_round_ph (m32, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c new file mode 100644 index 0000000..7c7288d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c @@ -0,0 +1,94 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define DEBUG + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(scalef_ph) (V512 * dest, V512 op1, V512 op2, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = v1.f32[i] * powf(2.0f, floorf(v3.f32[i])); + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = v2.f32[i] * powf(2.0f, floorf(v4.f32[i])); + } + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(scalef_ph) (&exp, src1, src2, NET_MASK, 0); + HF(res) = INTRINSIC (_scalef_ph) (HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _scalef_ph); + + init_dest(&res, &exp); + EMULATE(scalef_ph) (&exp, src1, src2, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_scalef_ph) (HF(res), MASK_VALUE, HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_scalef_ph); + + EMULATE(scalef_ph) (&exp, src1, src2, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_scalef_ph) (ZMASK_VALUE, HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_scalef_ph); + +#if AVX512F_LEN == 512 + EMULATE(scalef_ph) (&exp, src1, src2, NET_MASK, 0); + HF(res) = INTRINSIC (_scalef_round_ph) (HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _scalef_round_ph); + + init_dest(&res, &exp); + EMULATE(scalef_ph) (&exp, src1, src2, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_scalef_round_ph) (HF(res), MASK_VALUE, HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_scalef_round_ph); + + EMULATE(scalef_ph) (&exp, src1, src2, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_scalef_round_ph) (ZMASK_VALUE, HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_scalef_round_ph); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c new file mode 100644 index 0000000..999c048 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_scalef_sh (x1, x2); + res = _mm_mask_scalef_sh (res, m8, x1, x2); + res = _mm_maskz_scalef_sh (m8, x1, x2); + res = _mm_scalef_round_sh (x1, x2, 4); + res = _mm_mask_scalef_round_sh (res, m8, x1, x2, 8); + res = _mm_maskz_scalef_round_sh (m8, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c new file mode 100644 index 0000000..5db7be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c @@ -0,0 +1,58 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_scalef_sh(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = v1.f32[0] * powf(2.0f, floorf(v3.f32[0])); + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_scalef_sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_scalef_round_sh(src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_scalef_round_sh"); + + init_dest(&res, &exp); + emulate_scalef_sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_mask_scalef_round_sh(res.xmmh[0], 0x1, src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_mask_scalef_round_sh"); + + emulate_scalef_sh(&exp, src1, src2, 0x3, 1); + res.xmmh[0] = _mm_maskz_scalef_round_sh(0x3, src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_scalef_round_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1a.c new file mode 100644 index 0000000..497b5ba --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m512h res; +volatile __m512h x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_sqrt_ph (x1); + res = _mm512_mask_sqrt_ph (res, m32, x1); + res = _mm512_maskz_sqrt_ph (m32, x1); + res = _mm512_sqrt_round_ph (x1, 4); + res = _mm512_mask_sqrt_round_ph (res, m32, x1, 8); + res = _mm512_maskz_sqrt_round_ph (m32, x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1b.c new file mode 100644 index 0000000..d4d047b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtph-1b.c @@ -0,0 +1,92 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(sqrt_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = sqrtf(v1.f32[i]); + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = sqrtf(v2.f32[i]); + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(sqrt_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_sqrt_ph) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _sqrt_ph); + + init_dest(&res, &exp); + EMULATE(sqrt_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_sqrt_ph) (HF(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_sqrt_ph); + + EMULATE(sqrt_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_sqrt_ph) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_sqrt_ph); + +#if AVX512F_LEN == 512 + EMULATE(sqrt_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_sqrt_round_ph) (HF(src1), 8); + CHECK_RESULT (&res, &exp, N_ELEMS, _sqrt_round_ph); + + init_dest(&res, &exp); + EMULATE(sqrt_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_sqrt_round_ph) (HF(res), MASK_VALUE, HF(src1), 8); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_sqrt_round_ph); + + EMULATE(sqrt_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_sqrt_round_ph) (ZMASK_VALUE, HF(src1), 8); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_sqrt_round_ph); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1a.c new file mode 100644 index 0000000..dd44534 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1a.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtsh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtsh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_sqrt_sh (x1, x2); + res = _mm_mask_sqrt_sh (res, m8, x1, x2); + res = _mm_maskz_sqrt_sh (m8, x1, x2); + res = _mm_sqrt_round_sh (x1, x2, 4); + res = _mm_mask_sqrt_round_sh (res, m8, x1, x2, 8); + res = _mm_maskz_sqrt_round_sh (m8, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1b.c new file mode 100644 index 0000000..4744c6f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vsqrtsh-1b.c @@ -0,0 +1,60 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_sqrt_sh(V512 * dest, V512 op1, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = sqrtf(v1.f32[0]); + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_sqrt_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_sqrt_round_sh(exp.xmmh[0], src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_sqrt_round_sh"); + + init_dest(&res, &exp); + emulate_sqrt_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_sqrt_round_sh(res.xmmh[0], 0x1, exp.xmmh[0], + src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_mask_sqrt_round_sh"); + + emulate_sqrt_sh(&exp, src1, 0x1, 1); + res.xmmh[0] = _mm_maskz_sqrt_round_sh(0x1, exp.xmmh[0], src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_sqrt_round_sh"); + + if (n_errs != 0) { + abort (); + } + +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-1.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-1.c new file mode 100644 index 0000000..3621bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-1.c @@ -0,0 +1,55 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +void +test_512 (void) +{ + V512 res; + res.xmm[0] = _mm_castph_ps (src1.xmmh[0]); + check_results (&res, &src1, 8, "_mm_castph_ps"); + + res.xmmd[0] = _mm_castph_pd (src1.xmmh[0]); + check_results (&res, &src1, 8, "_mm_castph_pd"); + + res.xmmi[0] = _mm_castph_si128 (src1.xmmh[0]); + check_results (&res, &src1, 8, "_mm_castph_si128"); + + res.xmmh[0] = _mm_castps_ph (src1.xmm[0]); + check_results (&res, &src1, 8, "_mm_castps_ph"); + + res.xmmh[0] = _mm_castpd_ph (src1.xmmd[0]); + check_results (&res, &src1, 8, "_mm_castpd_ph"); + + res.xmmh[0] = _mm_castsi128_ph (src1.xmmi[0]); + check_results (&res, &src1, 8, "_mm_castsi128_ph"); + + res.ymm[0] = _mm256_castph_ps (src1.ymmh[0]); + check_results (&res, &src1, 16, "_mm256_castph_ps"); + + res.ymmd[0] = _mm256_castph_pd (src1.ymmh[0]); + check_results (&res, &src1, 16, "_mm256_castph_pd"); + + res.ymmi[0] = _mm256_castph_si256 (src1.ymmh[0]); + check_results (&res, &src1, 16, "_mm256_castph_si256"); + + res.ymmh[0] = _mm256_castps_ph (src1.ymm[0]); + check_results (&res, &src1, 16, "_mm256_castps_ph"); + + res.ymmh[0] = _mm256_castpd_ph (src1.ymmd[0]); + check_results (&res, &src1, 16, "_mm256_castpd_ph"); + + res.ymmh[0] = _mm256_castsi256_ph (src1.ymmi[0]); + check_results (&res, &src1, 16, "_mm256_castsi256_ph"); + + res.xmmh[0] = _mm256_castph256_ph128 (src1.ymmh[0]); + check_results (&res, &src1, 8, "_mm256_castph256_ph128"); + + res.ymmh[0] = _mm256_castph128_ph256 (src1.xmmh[0]); + check_results (&res, &src1, 8, "_mm256_castph128_ph256"); + + if (n_errs != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-2.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-2.c new file mode 100644 index 0000000..dce387f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-typecast-2.c @@ -0,0 +1,37 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +static void do_test (void); + +#define DO_TEST do_test +#define AVX512FP16 +#include "avx512f-check.h" + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); + +void +do_test (void) +{ + union512i_d zero; + union512h ad; + union256h b,bd; + union128h c; + + int i; + + for (i = 0; i < 16; i++) + { + b.a[i] = 65.43f + i; + zero.a[i] = 0; + } + + for (i = 0; i < 8; i++) + { + c.a[i] = 32.01f + i; + } + + bd.x = _mm256_zextph128_ph256 (c.x); + if (memcmp (bd.a, c.a, 16) + || memcmp (&bd.a[8], &zero.a, 16)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c new file mode 100644 index 0000000..ab0541d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepi32_ph (x2); + res3 = _mm256_mask_cvtepi32_ph (res3, m8, x2); + res3 = _mm256_maskz_cvtepi32_ph (m8, x2); + + res3 = _mm_cvtepi32_ph (x3); + res3 = _mm_mask_cvtepi32_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi32_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c new file mode 100644 index 0000000..033587a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtdq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtdq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1a.c new file mode 100644 index 0000000..57604a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256d x2; +volatile __m128d x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtpd_ph (x2); + res3 = _mm256_mask_cvtpd_ph (res3, m16, x2); + res3 = _mm256_maskz_cvtpd_ph (m16, x2); + + res3 = _mm_cvtpd_ph (x3); + res3 = _mm_mask_cvtpd_ph (res3, m8, x3); + res3 = _mm_maskz_cvtpd_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1b.c new file mode 100644 index 0000000..ea4b200 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtpd2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtpd2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtpd2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c new file mode 100644 index 0000000..df653b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi32 (x3); + res1 = _mm256_mask_cvtph_epi32 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epi32 (m8, x3); + + res2 = _mm_cvtph_epi32 (x3); + res2 = _mm_mask_cvtph_epi32 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epi32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c new file mode 100644 index 0000000..93a3e90 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2dq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2dq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1a.c new file mode 100644 index 0000000..80010c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256d res1; +volatile __m128d res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_pd (x3); + res1 = _mm256_mask_cvtph_pd (res1, m8, x3); + res1 = _mm256_maskz_cvtph_pd (m8, x3); + + res2 = _mm_cvtph_pd (x3); + res2 = _mm_mask_cvtph_pd (res2, m8, x3); + res2 = _mm_maskz_cvtph_pd (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1b.c new file mode 100644 index 0000000..a384905 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2pd-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2pd-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2pd-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1a.c new file mode 100644 index 0000000..e8c4c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256 res1; +volatile __m128 res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtxph_ps (x3); + res1 = _mm256_mask_cvtxph_ps (res1, m8, x3); + res1 = _mm256_maskz_cvtxph_ps (m8, x3); + + res2 = _mm_cvtxph_ps (x3); + res2 = _mm_mask_cvtxph_ps (res2, m8, x3); + res2 = _mm_maskz_cvtxph_ps (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1b.c new file mode 100644 index 0000000..ad91de8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2psx-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2psx-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2psx-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c new file mode 100644 index 0000000..ddc6f2a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi64 (x3); + res1 = _mm256_mask_cvtph_epi64 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epi64 (m8, x3); + + res2 = _mm_cvtph_epi64 (x3); + res2 = _mm_mask_cvtph_epi64 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epi64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c new file mode 100644 index 0000000..5afc5a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2qq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2qq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c new file mode 100644 index 0000000..d07d766 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu32 (x3); + res1 = _mm256_mask_cvtph_epu32 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epu32 (m8, x3); + + res2 = _mm_cvtph_epu32 (x3); + res2 = _mm_mask_cvtph_epu32 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epu32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c new file mode 100644 index 0000000..d869a0c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2udq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2udq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c new file mode 100644 index 0000000..26dbf22 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu64 (x3); + res1 = _mm256_mask_cvtph_epu64 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epu64 (m8, x3); + + res2 = _mm_cvtph_epu64 (x3); + res2 = _mm_mask_cvtph_epu64 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epu64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c new file mode 100644 index 0000000..d9b10a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uqq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uqq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c new file mode 100644 index 0000000..0f9fd27 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu16 (x3); + res1 = _mm256_mask_cvtph_epu16 (res1, m16, x3); + res1 = _mm256_maskz_cvtph_epu16 (m16, x3); + + res2 = _mm_cvtph_epu16 (x4); + res2 = _mm_mask_cvtph_epu16 (res2, m8, x4); + res2 = _mm_maskz_cvtph_epu16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c new file mode 100644 index 0000000..280dcd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uw-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uw-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c new file mode 100644 index 0000000..8dee4ee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi16 (x3); + res1 = _mm256_mask_cvtph_epi16 (res1, m16, x3); + res1 = _mm256_maskz_cvtph_epi16 (m16, x3); + + res2 = _mm_cvtph_epi16 (x4); + res2 = _mm_mask_cvtph_epi16 (res2, m8, x4); + res2 = _mm_maskz_cvtph_epi16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c new file mode 100644 index 0000000..739ba64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2w-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2w-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1a.c new file mode 100644 index 0000000..a89f8c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256 x2; +volatile __m128 x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtxps_ph (x2); + res3 = _mm256_mask_cvtxps_ph (res3, m8, x2); + res3 = _mm256_maskz_cvtxps_ph (m8, x2); + + res3 = _mm_cvtxps_ph (x3); + res3 = _mm_mask_cvtxps_ph (res3, m8, x3); + res3 = _mm_maskz_cvtxps_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1b.c new file mode 100644 index 0000000..a339d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtps2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtps2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtps2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c new file mode 100644 index 0000000..8e42a4b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepi64_ph (x2); + res3 = _mm256_mask_cvtepi64_ph (res3, m16, x2); + res3 = _mm256_maskz_cvtepi64_ph (m16, x2); + + res3 = _mm_cvtepi64_ph (x3); + res3 = _mm_mask_cvtepi64_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi64_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c new file mode 100644 index 0000000..6a4a329 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtqq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtqq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c new file mode 100644 index 0000000..b4c0840 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epi32 (x3); + res1 = _mm256_mask_cvttph_epi32 (res1, m8, x3); + res1 = _mm256_maskz_cvttph_epi32 (m8, x3); + + res2 = _mm_cvttph_epi32 (x3); + res2 = _mm_mask_cvttph_epi32 (res2, m8, x3); + res2 = _mm_maskz_cvttph_epi32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c new file mode 100644 index 0000000..f9d82f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2dq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2dq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c new file mode 100644 index 0000000..421c688 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epi64 (x3); + res1 = _mm256_mask_cvttph_epi64 (res1, m8, x3); + res1 = _mm256_maskz_cvttph_epi64 (m8, x3); + + res2 = _mm_cvttph_epi64 (x3); + res2 = _mm_mask_cvttph_epi64 (res2, m8, x3); + res2 = _mm_maskz_cvttph_epi64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c new file mode 100644 index 0000000..323ab74 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2qq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2qq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c new file mode 100644 index 0000000..60f4318 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epu32 (x3); + res1 = _mm256_mask_cvttph_epu32 (res1, m8, x3); + res1 = _mm256_maskz_cvttph_epu32 (m8, x3); + + res2 = _mm_cvttph_epu32 (x3); + res2 = _mm_mask_cvttph_epu32 (res2, m8, x3); + res2 = _mm_maskz_cvttph_epu32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c new file mode 100644 index 0000000..61365d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2udq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2udq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c new file mode 100644 index 0000000..37008f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epu64 (x3); + res1 = _mm256_mask_cvttph_epu64 (res1, m8, x3); + res1 = _mm256_maskz_cvttph_epu64 (m8, x3); + + res2 = _mm_cvttph_epu64 (x3); + res2 = _mm_mask_cvttph_epu64 (res2, m8, x3); + res2 = _mm_maskz_cvttph_epu64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c new file mode 100644 index 0000000..6360402 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2uqq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2uqq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c new file mode 100644 index 0000000..eafa31a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epu16 (x3); + res1 = _mm256_mask_cvttph_epu16 (res1, m16, x3); + res1 = _mm256_maskz_cvttph_epu16 (m16, x3); + + res2 = _mm_cvttph_epu16 (x4); + res2 = _mm_mask_cvttph_epu16 (res2, m8, x4); + res2 = _mm_maskz_cvttph_epu16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c new file mode 100644 index 0000000..dd5ed9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2uw-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2uw-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c new file mode 100644 index 0000000..7476d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvttph_epi16 (x3); + res1 = _mm256_mask_cvttph_epi16 (res1, m16, x3); + res1 = _mm256_maskz_cvttph_epi16 (m16, x3); + + res2 = _mm_cvttph_epi16 (x4); + res2 = _mm_mask_cvttph_epi16 (res2, m8, x4); + res2 = _mm_maskz_cvttph_epi16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c new file mode 100644 index 0000000..7a04a6a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2w-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvttph2w-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c new file mode 100644 index 0000000..4fa2ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepu32_ph (x2); + res3 = _mm256_mask_cvtepu32_ph (res3, m8, x2); + res3 = _mm256_maskz_cvtepu32_ph (m8, x2); + + res3 = _mm_cvtepu32_ph (x3); + res3 = _mm_mask_cvtepu32_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu32_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c new file mode 100644 index 0000000..4ea2c26 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtudq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtudq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c new file mode 100644 index 0000000..a3ee951 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepu64_ph (x2); + res3 = _mm256_mask_cvtepu64_ph (res3, m16, x2); + res3 = _mm256_maskz_cvtepu64_ph (m16, x2); + + res3 = _mm_cvtepu64_ph (x3); + res3 = _mm_mask_cvtepu64_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu64_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c new file mode 100644 index 0000000..c747e8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuqq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuqq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c new file mode 100644 index 0000000..59393dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res2; +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res2 = _mm256_cvtepu16_ph (x2); + res2 = _mm256_mask_cvtepu16_ph (res2, m16, x2); + res2 = _mm256_maskz_cvtepu16_ph (m16, x2); + + res3 = _mm_cvtepu16_ph (x3); + res3 = _mm_mask_cvtepu16_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu16_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c new file mode 100644 index 0000000..89d94df --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuw2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuw2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c new file mode 100644 index 0000000..ff5530f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res2; +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res2 = _mm256_cvtepi16_ph (x2); + res2 = _mm256_mask_cvtepi16_ph (res2, m16, x2); + res2 = _mm256_maskz_cvtepi16_ph (m16, x2); + + res3 = _mm_cvtepi16_ph (x3); + res3 = _mm_mask_cvtepi16_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi16_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c new file mode 100644 index 0000000..243e45b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtw2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtw2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1a.c new file mode 100644 index 0000000..897a3c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1a.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vfpclassphy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassphx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassphy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassphx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h x256; +volatile __m128h x128; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512dq_test (void) +{ + m16 = _mm256_fpclass_ph_mask (x256, 13); + m8 = _mm_fpclass_ph_mask (x128, 13); + m16 = _mm256_mask_fpclass_ph_mask (2, x256, 13); + m8 = _mm_mask_fpclass_ph_mask (2, x128, 13); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1b.c new file mode 100644 index 0000000..6745f13 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfpclassph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vfpclassph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1a.c new file mode 100644 index 0000000..82c23b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1a.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1} } */ +/* { dg-final { scan-assembler-times "vgetexpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1} } */ + +#include <immintrin.h> + +volatile __m256h xx; +volatile __m128h x2; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx512vl_test (void) +{ + xx = _mm256_getexp_ph (xx); + xx = _mm256_mask_getexp_ph (xx, m16, xx); + xx = _mm256_maskz_getexp_ph (m16, xx); + x2 = _mm_getexp_ph (x2); + x2 = _mm_mask_getexp_ph (x2, m8, x2); + x2 = _mm_maskz_getexp_ph (m8, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1b.c new file mode 100644 index 0000000..7eb4fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vgetexpph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vgetexpph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1a.c new file mode 100644 index 0000000..4ce6ed5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1a.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mavx512fp16 " } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgetmantph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h x, y; +volatile __m128h a, b; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx512vl_test (void) +{ + x = _mm256_getmant_ph (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + x = _mm256_mask_getmant_ph (x, m16, y, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); + x = _mm256_maskz_getmant_ph (m16, y, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); + a = _mm_getmant_ph (b, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src); + a = _mm_mask_getmant_ph (a, m8, b, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); + a = _mm_maskz_getmant_ph (m8, b, _MM_MANT_NORM_p75_1p5, + _MM_MANT_SIGN_src); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1b.c new file mode 100644 index 0000000..e5f8740 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vgetmantph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vgetmantph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c new file mode 100644 index 0000000..5894dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1; +volatile __m128h x2; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_rcp_ph (x1); + res1 = _mm256_mask_rcp_ph (res1, m16, x1); + res1 = _mm256_maskz_rcp_ph (m16, x1); + + res2 = _mm_rcp_ph (x2); + res2 = _mm_mask_rcp_ph (res2, m8, x2); + res2 = _mm_maskz_rcp_ph (m8, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c new file mode 100644 index 0000000..a6b1e37 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrcpph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrcpph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c new file mode 100644 index 0000000..4f43abd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +#define IMM 123 + +volatile __m256h x2; +volatile __m128h x3; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx512fp16_test (void) +{ + x2 = _mm256_reduce_ph (x2, IMM); + x3 = _mm_reduce_ph (x3, IMM); + + x2 = _mm256_mask_reduce_ph (x2, m16, x2, IMM); + x3 = _mm_mask_reduce_ph (x3, m8, x3, IMM); + + x2 = _mm256_maskz_reduce_ph (m8, x2, IMM); + x3 = _mm_maskz_reduce_ph (m16, x3, IMM); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c new file mode 100644 index 0000000..3851597 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vreduceph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vreduceph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c new file mode 100644 index 0000000..9fcf7e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +#define IMM 123 + +volatile __m256h x2; +volatile __m128h x3; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx512fp16_test (void) +{ + x2 = _mm256_roundscale_ph (x2, IMM); + x3 = _mm_roundscale_ph (x3, IMM); + + x2 = _mm256_mask_roundscale_ph (x2, m16, x2, IMM); + x3 = _mm_mask_roundscale_ph (x3, m8, x3, IMM); + + x2 = _mm256_maskz_roundscale_ph (m8, x2, IMM); + x3 = _mm_maskz_roundscale_ph (m16, x3, IMM); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c new file mode 100644 index 0000000..04b00e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrndscaleph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrndscaleph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c new file mode 100644 index 0000000..a5edc17 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1; +volatile __m128h x2; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_rsqrt_ph (x1); + res1 = _mm256_mask_rsqrt_ph (res1, m16, x1); + res1 = _mm256_maskz_rsqrt_ph (m16, x1); + + res2 = _mm_rsqrt_ph (x2); + res2 = _mm_mask_rsqrt_ph (res2, m8, x2); + res2 = _mm_maskz_rsqrt_ph (m8, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c new file mode 100644 index 0000000..a5e796b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrsqrtph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrsqrtph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c new file mode 100644 index 0000000..22231d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1,x2; +volatile __m128h x3, x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_scalef_ph (x1, x2); + res1 = _mm256_mask_scalef_ph (res1, m16, x1, x2); + res1 = _mm256_maskz_scalef_ph (m16, x1, x2); + + res2 = _mm_scalef_ph (x3, x4); + res2 = _mm_mask_scalef_ph (res2, m8, x3, x4); + res2 = _mm_maskz_scalef_ph (m8, x3, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c new file mode 100644 index 0000000..5c12d08 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vscalefph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vscalefph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1a.c new file mode 100644 index 0000000..4acb137 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vsqrtph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1; +volatile __m128h x2; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_sqrt_ph (x1); + res1 = _mm256_mask_sqrt_ph (res1, m16, x1); + res1 = _mm256_maskz_sqrt_ph (m16, x1); + + res2 = _mm_sqrt_ph (x2); + res2 = _mm_mask_sqrt_ph (res2, m8, x2); + res2 = _mm_maskz_sqrt_ph (m8, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1b.c new file mode 100644 index 0000000..9b0a91d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vsqrtph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vsqrtph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/pr101900-1.c b/gcc/testsuite/gcc.target/i386/pr101900-1.c new file mode 100644 index 0000000..0a45f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101900-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=use_vector_fp_converts" } */ + +extern float f; +extern double d; +extern int i; + +void +foo (void) +{ + d = f; + f = i; +} + +/* { dg-final { scan-assembler "vcvtps2pd" } } */ +/* { dg-final { scan-assembler "vcvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "vcvtss2sd" } } */ +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr101900-2.c b/gcc/testsuite/gcc.target/i386/pr101900-2.c new file mode 100644 index 0000000..c8b2d1d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101900-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=use_vector_converts" } */ + +extern float f; +extern double d; +extern int i; + +void +foo (void) +{ + d = f; + f = i; +} + +/* { dg-final { scan-assembler "vcvtss2sd" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps" } } */ +/* { dg-final { scan-assembler-not "vcvtsi2ssl" } } */ +/* { dg-final { scan-assembler-times "vxorps\[^\n\r\]*xmm\[0-9\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr101900-3.c b/gcc/testsuite/gcc.target/i386/pr101900-3.c new file mode 100644 index 0000000..6ee565b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101900-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake -mfpmath=sse -mtune-ctrl=use_vector_fp_converts,use_vector_converts" } */ + +extern float f; +extern double d; +extern int i; + +void +foo (void) +{ + d = f; + f = i; +} + +/* { dg-final { scan-assembler "vcvtps2pd" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps" } } */ +/* { dg-final { scan-assembler-not "vcvtss2sd" } } */ +/* { dg-final { scan-assembler-not "vcvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "vxorps" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr102080.c b/gcc/testsuite/gcc.target/i386/pr102080.c new file mode 100644 index 0000000..4c5ee32 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102080.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include<immintrin.h> +typedef float __m256 __attribute__((__vector_size__(32))); +__m256 _mm256_blendv_ps___Y, _mm256_blendv_ps___M, _mm256_mul_ps___A, + _mm256_mul_ps___B, IfThenElse___trans_tmp_9; + +void +__attribute__ ((target("avx"))) +IfThenElse (__m256 no) { + IfThenElse___trans_tmp_9 = _mm256_blendv_ps (no, _mm256_blendv_ps___Y, _mm256_blendv_ps___M); +} +void +__attribute__ ((target("avx512vl"))) +EncodedFromDisplay() { + __m256 __trans_tmp_11 = _mm256_mul_ps___A * _mm256_mul_ps___B; + IfThenElse(__trans_tmp_11); +} diff --git a/gcc/testsuite/gcc.target/i386/pr102327-1.c b/gcc/testsuite/gcc.target/i386/pr102327-1.c new file mode 100644 index 0000000..4743926 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102327-1.c @@ -0,0 +1,65 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ + +typedef _Float16 v8hf __attribute__((vector_size (16))); +typedef _Float16 v16hf __attribute__((vector_size (32))); +typedef _Float16 v32hf __attribute__((vector_size (64))); + +#define VEC_EXTRACT(V,S,IDX) \ + S \ + __attribute__((noipa)) \ + vec_extract_##V##_##IDX (V v) \ + { \ + return v[IDX]; \ + } + +#define VEC_SET(V,S,IDX) \ + V \ + __attribute__((noipa)) \ + vec_set_##V##_##IDX (V v, S s) \ + { \ + v[IDX] = s; \ + return v; \ + } + +v8hf +vec_init_v8hf (_Float16 a1, _Float16 a2, _Float16 a3, _Float16 a4, _Float16 a5, +_Float16 a6, _Float16 a7, _Float16 a8) +{ + return __extension__ (v8hf) {a1, a2, a3, a4, a5, a6, a7, a8}; +} + +/* { dg-final { scan-assembler-times "vpunpcklwd" 4 } } */ +/* { dg-final { scan-assembler-times "vpunpckldq" 2 } } */ +/* { dg-final { scan-assembler-times "vpunpcklqdq" 1 } } */ + +VEC_EXTRACT (v8hf, _Float16, 4); +VEC_EXTRACT (v16hf, _Float16, 3); +VEC_EXTRACT (v16hf, _Float16, 8); +VEC_EXTRACT (v16hf, _Float16, 15); +VEC_EXTRACT (v32hf, _Float16, 5); +VEC_EXTRACT (v32hf, _Float16, 8); +VEC_EXTRACT (v32hf, _Float16, 14); +VEC_EXTRACT (v32hf, _Float16, 16); +VEC_EXTRACT (v32hf, _Float16, 24); +VEC_EXTRACT (v32hf, _Float16, 28); +/* { dg-final { scan-assembler-times "vpsrldq\[\t ]*\\\$8" 2 } } */ +/* { dg-final { scan-assembler-times "vpsrldq\[\t ]*\\\$6" 1 } } */ +/* { dg-final { scan-assembler-times "vpsrldq\[\t ]*\\\$14" 1 } } */ +/* { dg-final { scan-assembler-times "vpsrldq\[\t ]*\\\$10" 1 } } */ +/* { dg-final { scan-assembler-times "vpsrldq\[\t ]*\\\$12" 1 } } */ +/* { dg-final { scan-assembler-times "vextract" 9 } } */ + +VEC_SET (v8hf, _Float16, 4); +VEC_SET (v16hf, _Float16, 3); +VEC_SET (v16hf, _Float16, 8); +VEC_SET (v16hf, _Float16, 15); +VEC_SET (v32hf, _Float16, 5); +VEC_SET (v32hf, _Float16, 8); +VEC_SET (v32hf, _Float16, 14); +VEC_SET (v32hf, _Float16, 16); +VEC_SET (v32hf, _Float16, 24); +VEC_SET (v32hf, _Float16, 28); +/* { dg-final { scan-assembler-times "vpbroadcastw" 10 } } */ +/* { dg-final { scan-assembler-times "vpblendw" 4 } } */ +/* { dg-final { scan-assembler-times "vpblendd" 3 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr102327-2.c b/gcc/testsuite/gcc.target/i386/pr102327-2.c new file mode 100644 index 0000000..363e4b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102327-2.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mavx512fp16" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512fp16 } */ + +#define AVX512VL +#define AVX512FP16 + +#ifndef CHECK +#define CHECK "avx512f-helper.h" +#endif + +#include CHECK +#include "pr102327-1.c" + +#define RUNCHECK_VEC_EXTRACT(U,V,S,IDX) \ + do \ + { \ + S tmp = vec_extract_##V##_##IDX ((V)U.x); \ + if (tmp != U.a[IDX]) \ + abort(); \ + } \ + while (0) + +#define RUNCHECK_VEC_SET(UTYPE,U,V,S,IDX,NUM) \ + do \ + { \ + S tmp = 3.0f; \ + UTYPE res; \ + res.x = vec_set_##V##_##IDX ((V)U.x, tmp); \ + for (int i = 0; i != NUM; i++) \ + if (i == IDX) \ + { \ + if (res.a[i] != tmp) \ + abort (); \ + } \ + else if (res.a[i] != U.a[i]) \ + abort(); \ + } \ + while (0) + +void +test_256 (void) +{ + union512h g1; + union256h t1; + union128h x1; + int sign = 1; + + int i = 0; + for (i = 0; i < 32; i++) + { + g1.a[i] = 56.78 * (i - 30) * sign; + sign = -sign; + } + + for (i = 0; i != 16; i++) + { + t1.a[i] = 90.12 * (i + 40) * sign; + sign = -sign; + } + + for (i = 0; i != 8; i++) + { + x1.a[i] = 90.12 * (i + 40) * sign; + sign = -sign; + } + + RUNCHECK_VEC_EXTRACT (x1, v8hf, _Float16, 4); + RUNCHECK_VEC_EXTRACT (t1, v16hf, _Float16, 3); + RUNCHECK_VEC_EXTRACT (t1, v16hf, _Float16, 8); + RUNCHECK_VEC_EXTRACT (t1, v16hf, _Float16, 15); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 5); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 8); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 14); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 16); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 24); + RUNCHECK_VEC_EXTRACT (g1, v32hf, _Float16, 28); + + RUNCHECK_VEC_SET (union128h, x1, v8hf, _Float16, 4, 8); + RUNCHECK_VEC_SET (union256h, t1, v16hf, _Float16, 3, 16); + RUNCHECK_VEC_SET (union256h, t1, v16hf, _Float16, 8, 16); + RUNCHECK_VEC_SET (union256h, t1, v16hf, _Float16, 15, 16); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 5, 32); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 8, 32); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 14, 32); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 16, 32); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 24, 32); + RUNCHECK_VEC_SET (union512h, g1, v32hf, _Float16, 28, 32); +} + +void +test_128() +{ +} diff --git a/gcc/testsuite/gcc.target/i386/pr91103-1.c b/gcc/testsuite/gcc.target/i386/pr91103-1.c index 11caaa8..2d78a6d 100644 --- a/gcc/testsuite/gcc.target/i386/pr91103-1.c +++ b/gcc/testsuite/gcc.target/i386/pr91103-1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -O2" } */ -/* { dg-final { scan-assembler-times "valign\[dq\]" 16 } } */ +/* { dg-final { scan-assembler-times "valign\[dq\]" 8 } } */ +/* { dg-final { scan-assembler-times "vextract" 12 } } */ typedef float v8sf __attribute__((vector_size(32))); typedef float v16sf __attribute__((vector_size(64))); @@ -23,9 +24,13 @@ EXTRACT (v8sf, float, 4); EXTRACT (v8sf, float, 7); EXTRACT (v8si, int, 4); EXTRACT (v8si, int, 7); +EXTRACT (v16sf, float, 4); EXTRACT (v16sf, float, 8); +EXTRACT (v16sf, float, 12); EXTRACT (v16sf, float, 15); +EXTRACT (v16si, int, 4); EXTRACT (v16si, int, 8); +EXTRACT (v16si, int, 12); EXTRACT (v16si, int, 15); EXTRACT (v4df, double, 2); EXTRACT (v4df, double, 3); diff --git a/gcc/testsuite/gcc.target/i386/pr91103-2.c b/gcc/testsuite/gcc.target/i386/pr91103-2.c index 010e477..a928d87 100644 --- a/gcc/testsuite/gcc.target/i386/pr91103-2.c +++ b/gcc/testsuite/gcc.target/i386/pr91103-2.c @@ -61,9 +61,13 @@ RUNCHECK (f2, v8sf, float, 4); RUNCHECK (f2, v8sf, float, 7); RUNCHECK (di2, v8si, int, 4); RUNCHECK (di2, v8si, int, 7); +RUNCHECK (f1, v16sf, float, 4); RUNCHECK (f1, v16sf, float, 8); +RUNCHECK (f1, v16sf, float, 12); RUNCHECK (f1, v16sf, float, 15); +RUNCHECK (di1, v16si, int, 4); RUNCHECK (di1, v16si, int, 8); +RUNCHECK (di1, v16si, int, 12); RUNCHECK (di1, v16si, int, 15); RUNCHECK (d2, v4df, double, 2); RUNCHECK (d2, v4df, double, 3); diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 9a2833d..dd33993 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -703,25 +703,85 @@ #define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E) /* avx512fp16intrin.h */ -#define __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vcmpph_v32hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v32hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpph_v32hf_mask_round(A, B, 1, D, 8) -#define __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_addph512_mask_round(A, B, C, D, E) __builtin_ia32_addph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subph512_mask_round(A, B, C, D, E) __builtin_ia32_subph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulph512_mask_round(A, B, C, D, E) __builtin_ia32_mulph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divph512_mask_round(A, B, C, D, E) __builtin_ia32_divph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_addsh_mask_round(A, B, C, D, E) __builtin_ia32_addsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subsh_mask_round(A, B, C, D, E) __builtin_ia32_subsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulsh_mask_round(A, B, C, D, E) __builtin_ia32_mulsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divsh_mask_round(A, B, C, D, E) __builtin_ia32_divsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxph512_mask_round(A, B, C, D, E) __builtin_ia32_maxph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minph512_mask_round(A, B, C, D, E) __builtin_ia32_minph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxsh_mask_round(A, B, C, D, E) __builtin_ia32_maxsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minsh_mask_round(A, B, C, D, E) __builtin_ia32_minsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_cmpph512_mask(A, B, C, D) __builtin_ia32_cmpph512_mask(A, B, 1, D) +#define __builtin_ia32_cmpph512_mask_round(A, B, C, D, E) __builtin_ia32_cmpph512_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_cmpsh_mask_round(A, B, C, D, E) __builtin_ia32_cmpsh_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_sqrtph512_mask_round(C, A, B, D) __builtin_ia32_sqrtph512_mask_round(C, A, B, 8) +#define __builtin_ia32_sqrtsh_mask_round(D, C, A, B, E) __builtin_ia32_sqrtsh_mask_round(D, C, A, B, 8) +#define __builtin_ia32_scalefph512_mask_round(A, B, C, D, E) __builtin_ia32_scalefph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_scalefsh_mask_round(A, B, C, D, E) __builtin_ia32_scalefsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_reduceph512_mask_round(A, B, C, D, E) __builtin_ia32_reduceph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_reduceph128_mask(A, B, C, D) __builtin_ia32_reduceph128_mask(A, 123, C, D) +#define __builtin_ia32_reduceph256_mask(A, B, C, D) __builtin_ia32_reduceph256_mask(A, 123, C, D) +#define __builtin_ia32_reducesh_mask_round(A, B, C, D, E, F) __builtin_ia32_reducesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_rndscaleph512_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_rndscaleph128_mask(A, B, C, D) __builtin_ia32_rndscaleph128_mask(A, 123, C, D) +#define __builtin_ia32_rndscaleph256_mask(A, B, C, D) __builtin_ia32_rndscaleph256_mask(A, 123, C, D) +#define __builtin_ia32_rndscalesh_mask_round(A, B, C, D, E, F) __builtin_ia32_rndscalesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_fpclassph512_mask(A, D, C) __builtin_ia32_fpclassph512_mask(A, 1, C) +#define __builtin_ia32_fpclasssh_mask(A, D, U) __builtin_ia32_fpclasssh_mask(A, 1, U) +#define __builtin_ia32_getexpph512_mask(A, B, C, D) __builtin_ia32_getexpph512_mask(A, B, C, 8) +#define __builtin_ia32_getexpsh_mask_round(A, B, C, D, E) __builtin_ia32_getexpsh_mask_round(A, B, C, D, 4) +#define __builtin_ia32_getmantph512_mask(A, F, C, D, E) __builtin_ia32_getmantph512_mask(A, 1, C, D, 8) +#define __builtin_ia32_getmantsh_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsh_mask_round(A, B, 1, W, U, 4) +#define __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2si32_round(A, B) __builtin_ia32_vcvtsh2si32_round(A, 8) +#define __builtin_ia32_vcvtsh2si64_round(A, B) __builtin_ia32_vcvtsh2si64_round(A, 8) +#define __builtin_ia32_vcvtsh2usi32_round(A, B) __builtin_ia32_vcvtsh2usi32_round(A, 8) +#define __builtin_ia32_vcvtsh2usi64_round(A, B) __builtin_ia32_vcvtsh2usi64_round(A, 8) +#define __builtin_ia32_vcvttsh2si32_round(A, B) __builtin_ia32_vcvttsh2si32_round(A, 8) +#define __builtin_ia32_vcvttsh2si64_round(A, B) __builtin_ia32_vcvttsh2si64_round(A, 8) +#define __builtin_ia32_vcvttsh2usi32_round(A, B) __builtin_ia32_vcvttsh2usi32_round(A, 8) +#define __builtin_ia32_vcvttsh2usi64_round(A, B) __builtin_ia32_vcvttsh2usi64_round(A, 8) +#define __builtin_ia32_vcvtsi2sh32_round(A, B, C) __builtin_ia32_vcvtsi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtsi2sh64_round(A, B, C) __builtin_ia32_vcvtsi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh32_round(A, B, C) __builtin_ia32_vcvtusi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh64_round(A, B, C) __builtin_ia32_vcvtusi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, 8) /* avx512fp16vlintrin.h */ -#define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v16hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v16hf_mask(A, B, 1, D) +#define __builtin_ia32_cmpph128_mask(A, B, C, D) __builtin_ia32_cmpph128_mask(A, B, 1, D) +#define __builtin_ia32_cmpph256_mask(A, B, C, D) __builtin_ia32_cmpph256_mask(A, B, 1, D) +#define __builtin_ia32_fpclassph256_mask(A, D, C) __builtin_ia32_fpclassph256_mask(A, 1, C) +#define __builtin_ia32_fpclassph128_mask(A, D, C) __builtin_ia32_fpclassph128_mask(A, 1, C) +#define __builtin_ia32_getmantph256_mask(A, E, C, D) __builtin_ia32_getmantph256_mask(A, 1, C, D) +#define __builtin_ia32_getmantph128_mask(A, E, C, D) __builtin_ia32_getmantph128_mask(A, 1, C, D) /* vpclmulqdqintrin.h */ #define __builtin_ia32_vpclmulqdq_v4di(A, B, C) __builtin_ia32_vpclmulqdq_v4di(A, B, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index ce0ad71..e64321d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -670,6 +670,52 @@ test_3 (_mm512_mask_rsqrt28_round_pd, __m512d, __m512d, __mmask8, __m512d, 8) test_3 (_mm512_mask_rsqrt28_round_ps, __m512, __m512, __mmask16, __m512, 8) /* avx512fp16intrin.h */ +test_1 (_mm512_sqrt_round_ph, __m512h, __m512h, 8) +test_1 (_mm_reduce_ph, __m128h, __m128h, 123) +test_1 (_mm256_reduce_ph, __m256h, __m256h, 123) +test_1 (_mm512_reduce_ph, __m512h, __m512h, 123) +test_1 (_mm_roundscale_ph, __m128h, __m128h, 123) +test_1 (_mm256_roundscale_ph, __m256h, __m256h, 123) +test_1 (_mm512_roundscale_ph, __m512h, __m512h, 123) +test_1 (_mm512_getexp_round_ph, __m512h, __m512h, 8) +test_1 (_mm512_cvt_roundph_epi16, __m512i, __m512h, 8) +test_1 (_mm512_cvt_roundph_epu16, __m512i, __m512h, 8) +test_1 (_mm512_cvtt_roundph_epi16, __m512i, __m512h, 8) +test_1 (_mm512_cvtt_roundph_epu16, __m512i, __m512h, 8) +test_1 (_mm512_cvt_roundph_epi32, __m512i, __m256h, 8) +test_1 (_mm512_cvt_roundph_epu32, __m512i, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epi32, __m512i, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epu32, __m512i, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epi64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundph_pd, __m512d, __m128h, 8) +test_1 (_mm512_cvtx_roundph_ps, __m512, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epu64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundph_epi64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundph_epu64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundepi16_ph, __m512h, __m512i, 8) +test_1 (_mm512_cvt_roundepu16_ph, __m512h, __m512i, 8) +test_1 (_mm512_cvt_roundepi32_ph, __m256h, __m512i, 8) +test_1 (_mm512_cvt_roundepu32_ph, __m256h, __m512i, 8) +test_1 (_mm512_cvt_roundepi64_ph, __m128h, __m512i, 8) +test_1 (_mm512_cvt_roundepu64_ph, __m128h, __m512i, 8) +test_1 (_mm512_cvtx_roundps_ph, __m256h, __m512, 8) +test_1 (_mm512_cvt_roundpd_ph, __m128h, __m512d, 8) +test_1 (_mm_cvt_roundsh_i32, int, __m128h, 8) +test_1 (_mm_cvt_roundsh_u32, unsigned, __m128h, 8) +test_1 (_mm_cvtt_roundsh_i32, int, __m128h, 8) +test_1 (_mm_cvtt_roundsh_u32, unsigned, __m128h, 8) +#ifdef __x86_64__ +test_1 (_mm_cvt_roundsh_i64, long long, __m128h, 8) +test_1 (_mm_cvt_roundsh_u64, unsigned long long, __m128h, 8) +test_1 (_mm_cvtt_roundsh_i64, long long, __m128h, 8) +test_1 (_mm_cvtt_roundsh_u64, unsigned long long, __m128h, 8) +test_2 (_mm_cvt_roundi64_sh, __m128h, __m128h, long long, 8) +test_2 (_mm_cvt_roundu64_sh, __m128h, __m128h, unsigned long long, 8) +#endif +test_1x (_mm512_reduce_round_ph, __m512h, __m512h, 123, 8) +test_1x (_mm512_roundscale_round_ph, __m512h, __m512h, 123, 8) +test_1x (_mm512_getmant_ph, __m512h, __m512h, 1, 1) +test_1y (_mm512_getmant_round_ph, __m512h, __m512h, 1, 1, 8) test_2 (_mm512_add_round_ph, __m512h, __m512h, __m512h, 8) test_2 (_mm512_sub_round_ph, __m512h, __m512h, __m512h, 8) test_2 (_mm512_mul_round_ph, __m512h, __m512h, __m512h, 8) @@ -684,9 +730,59 @@ test_2 (_mm_max_round_sh, __m128h, __m128h, __m128h, 8) test_2 (_mm_min_round_sh, __m128h, __m128h, __m128h, 8) test_2 (_mm512_cmp_ph_mask, __mmask32, __m512h, __m512h, 1) test_2 (_mm_comi_sh, int, __m128h, __m128h, 1) +test_2 (_mm512_maskz_sqrt_round_ph, __m512h, __mmask32, __m512h, 8) +test_2 (_mm_sqrt_round_sh, __m128h, __m128h, __m128h, 8) +test_2 (_mm512_scalef_round_ph, __m512h, __m512h, __m512h, 8) +test_2 (_mm_scalef_round_sh, __m128h, __m128h, __m128h, 8) +test_2 (_mm_maskz_reduce_ph, __m128h, __mmask8, __m128h, 123) +test_2 (_mm256_maskz_reduce_ph, __m256h, __mmask16, __m256h, 123) +test_2 (_mm512_maskz_reduce_ph, __m512h, __mmask32, __m512h, 123) +test_2 (_mm_reduce_sh, __m128h, __m128h, __m128h, 123) +test_2 (_mm_maskz_roundscale_ph, __m128h, __mmask8, __m128h, 123) +test_2 (_mm256_maskz_roundscale_ph, __m256h, __mmask16, __m256h, 123) +test_2 (_mm512_maskz_roundscale_ph, __m512h, __mmask32, __m512h, 123) +test_2 (_mm_roundscale_sh, __m128h, __m128h, __m128h, 123) +test_2 (_mm512_maskz_getexp_round_ph, __m512h, __mmask32, __m512h, 8) +test_2 (_mm_getexp_round_sh, __m128h, __m128h, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_pd, __m512d, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvtx_roundph_ps, __m512, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundepi16_ph, __m512h, __mmask32, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu16_ph, __m512h, __mmask32, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepi32_ph, __m256h, __mmask16, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu32_ph, __m256h, __mmask16, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepi64_ph, __m128h, __mmask8, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu64_ph, __m128h, __mmask8, __m512i, 8) +test_2 (_mm512_maskz_cvtx_roundps_ph, __m256h, __mmask16, __m512, 8) +test_2 (_mm512_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m512d, 8) +test_2 (_mm_cvt_roundsh_ss, __m128, __m128, __m128h, 8) +test_2 (_mm_cvt_roundsh_sd, __m128d, __m128d, __m128h, 8) +test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8) +test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8) +test_2 (_mm_cvt_roundi32_sh, __m128h, __m128h, int, 8) +test_2 (_mm_cvt_roundu32_sh, __m128h, __m128h, unsigned, 8) test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8) test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8) test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8) +test_2x (_mm512_maskz_reduce_round_ph, __m512h, __mmask32, __m512h, 123, 8) +test_2x (_mm512_maskz_roundscale_round_ph, __m512h, __mmask32, __m512h, 123, 8) +test_2x (_mm_reduce_round_sh, __m128h, __m128h, __m128h, 123, 8) +test_2x (_mm_roundscale_round_sh, __m128h, __m128h, __m128h, 123, 8) +test_2x (_mm512_maskz_getmant_ph, __m512h, __mmask32, __m512h, 1, 1) +test_2x (_mm_getmant_sh, __m128h, __m128h, __m128h, 1, 1) +test_2y (_mm512_maskz_getmant_round_ph, __m512h, __mmask32, __m512h, 1, 1, 8) +test_2y (_mm_getmant_round_sh, __m128h, __m128h, __m128h, 1, 1, 8) test_3 (_mm512_maskz_add_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm512_maskz_sub_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm512_maskz_mul_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) @@ -700,8 +796,56 @@ test_3 (_mm512_maskz_min_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm_maskz_max_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) test_3 (_mm_maskz_min_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) test_3 (_mm512_mask_cmp_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1) +test_3 (_mm512_mask_sqrt_round_ph, __m512h, __m512h, __mmask32, __m512h, 8) +test_3 (_mm_maskz_sqrt_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) +test_3 (_mm512_maskz_scalef_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) +test_3 (_mm_maskz_scalef_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) +test_3 (_mm_mask_reduce_ph, __m128h, __m128h, __mmask8, __m128h, 123) +test_3 (_mm256_mask_reduce_ph, __m256h, __m256h, __mmask16, __m256h, 123) +test_3 (_mm512_mask_reduce_ph, __m512h, __m512h, __mmask32, __m512h, 123) +test_3 (_mm_maskz_reduce_sh, __m128h, __mmask8, __m128h, __m128h, 123) +test_3 (_mm_mask_roundscale_ph, __m128h, __m128h, __mmask8, __m128h, 123) +test_3 (_mm256_mask_roundscale_ph, __m256h, __m256h, __mmask16, __m256h, 123) +test_3 (_mm512_mask_roundscale_ph, __m512h, __m512h, __mmask32, __m512h, 123) +test_3 (_mm_maskz_roundscale_sh, __m128h, __mmask8, __m128h, __m128h, 123) +test_3 (_mm_maskz_getexp_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) +test_3 (_mm512_mask_getexp_round_ph, __m512h, __m512h, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epi16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epu16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epi32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvt_roundph_epu32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvt_roundph_epi64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundph_epu64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundph_pd, __m512d, __m512d, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvtx_roundph_ps, __m512, __m512, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundepi16_ph, __m512h, __m512h, __mmask32, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu16_ph, __m512h, __m512h, __mmask32, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepi32_ph, __m256h, __m256h, __mmask16, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu32_ph, __m256h, __m256h, __mmask16, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepi64_ph, __m128h, __m128h, __mmask8, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu64_ph, __m128h, __m128h, __mmask8, __m512i, 8) +test_3 (_mm512_mask_cvtx_roundps_ph, __m256h, __m256h, __mmask16, __m512, 8) +test_3 (_mm512_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m512d, 8) +test_3 (_mm_maskz_cvt_roundsh_ss, __m128, __mmask8, __m128, __m128h, 8) +test_3 (_mm_maskz_cvt_roundsh_sd, __m128d, __mmask8, __m128d, __m128h, 8) +test_3 (_mm_maskz_cvt_roundss_sh, __m128h, __mmask8, __m128h, __m128, 8) +test_3 (_mm_maskz_cvt_roundsd_sh, __m128h, __mmask8, __m128h, __m128d, 8) test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8) test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8) +test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) +test_3x (_mm512_mask_roundscale_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) +test_3x (_mm_maskz_reduce_round_sh, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_3x (_mm_maskz_roundscale_round_sh, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_3x (_mm512_mask_getmant_ph, __m512h, __m512h, __mmask32, __m512h, 1, 1) +test_3x (_mm_maskz_getmant_sh, __m128h, __mmask8, __m128h, __m128h, 1, 1) +test_3y (_mm_maskz_getmant_round_sh, __m128h, __mmask8, __m128h, __m128h, 1, 1, 8) +test_3y (_mm512_mask_getmant_round_ph, __m512h, __m512h, __mmask32, __m512h, 1, 1, 8) test_4 (_mm512_mask_add_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm512_mask_sub_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm512_mask_mul_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) @@ -714,6 +858,20 @@ test_4 (_mm512_mask_max_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, test_4 (_mm512_mask_min_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm_mask_max_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) test_4 (_mm_mask_min_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm_mask_sqrt_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm512_mask_scalef_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) +test_4 (_mm_mask_scalef_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm_mask_reduce_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123) +test_4 (_mm_mask_roundscale_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123) +test_4 (_mm_mask_getexp_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm_mask_cvt_roundsh_ss, __m128, __m128, __mmask8, __m128, __m128h, 8) +test_4 (_mm_mask_cvt_roundsh_sd, __m128d, __m128d, __mmask8, __m128d, __m128h, 8) +test_4 (_mm_mask_cvt_roundss_sh, __m128h, __m128h, __mmask8, __m128h, __m128, 8) +test_4 (_mm_mask_cvt_roundsd_sh, __m128h, __m128h, __mmask8, __m128h, __m128d, 8) +test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1) +test_4y (_mm_mask_getmant_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1, 8) /* avx512fp16vlintrin.h */ test_2 (_mm_cmp_ph_mask, __mmask8, __m128h, __m128h, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 4393464..d92898f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -775,6 +775,52 @@ test_2 (_mm_rsqrt28_round_sd, __m128d, __m128d, __m128d, 8) test_2 (_mm_rsqrt28_round_ss, __m128, __m128, __m128, 8) /* avx512fp16intrin.h */ +test_1 (_mm512_sqrt_round_ph, __m512h, __m512h, 8) +test_1 (_mm_reduce_ph, __m128h, __m128h, 123) +test_1 (_mm256_reduce_ph, __m256h, __m256h, 123) +test_1 (_mm512_reduce_ph, __m512h, __m512h, 123) +test_1 (_mm_roundscale_ph, __m128h, __m128h, 123) +test_1 (_mm256_roundscale_ph, __m256h, __m256h, 123) +test_1 (_mm512_roundscale_ph, __m512h, __m512h, 123) +test_1 (_mm512_getexp_round_ph, __m512h, __m512h, 8) +test_1 (_mm512_cvt_roundph_epi16, __m512i, __m512h, 8) +test_1 (_mm512_cvt_roundph_epu16, __m512i, __m512h, 8) +test_1 (_mm512_cvtt_roundph_epi16, __m512i, __m512h, 8) +test_1 (_mm512_cvtt_roundph_epu16, __m512i, __m512h, 8) +test_1 (_mm512_cvt_roundph_epi32, __m512i, __m256h, 8) +test_1 (_mm512_cvt_roundph_epu32, __m512i, __m256h, 8) +test_1 (_mm512_cvt_roundph_epi64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundph_epu64, __m512i, __m128h, 8) +test_1 (_mm512_cvtt_roundph_epi32, __m512i, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epu32, __m512i, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epi64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundph_pd, __m512d, __m128h, 8) +test_1 (_mm512_cvtx_roundph_ps, __m512, __m256h, 8) +test_1 (_mm512_cvtt_roundph_epu64, __m512i, __m128h, 8) +test_1 (_mm512_cvt_roundepi16_ph, __m512h, __m512i, 8) +test_1 (_mm512_cvt_roundepu16_ph, __m512h, __m512i, 8) +test_1 (_mm512_cvt_roundepi32_ph, __m256h, __m512i, 8) +test_1 (_mm512_cvt_roundepu32_ph, __m256h, __m512i, 8) +test_1 (_mm512_cvt_roundepi64_ph, __m128h, __m512i, 8) +test_1 (_mm512_cvt_roundepu64_ph, __m128h, __m512i, 8) +test_1 (_mm512_cvtx_roundps_ph, __m256h, __m512, 8) +test_1 (_mm512_cvt_roundpd_ph, __m128h, __m512d, 8) +test_1 (_mm_cvt_roundsh_i32, int, __m128h, 8) +test_1 (_mm_cvt_roundsh_u32, unsigned, __m128h, 8) +test_1 (_mm_cvtt_roundsh_i32, int, __m128h, 8) +test_1 (_mm_cvtt_roundsh_u32, unsigned, __m128h, 8) +#ifdef __x86_64__ +test_1 (_mm_cvt_roundsh_i64, long long, __m128h, 8) +test_1 (_mm_cvt_roundsh_u64, unsigned long long, __m128h, 8) +test_1 (_mm_cvtt_roundsh_i64, long long, __m128h, 8) +test_1 (_mm_cvtt_roundsh_u64, unsigned long long, __m128h, 8) +test_2 (_mm_cvt_roundi64_sh, __m128h, __m128h, long long, 8) +test_2 (_mm_cvt_roundu64_sh, __m128h, __m128h, unsigned long long, 8) +#endif +test_1x (_mm512_reduce_round_ph, __m512h, __m512h, 123, 8) +test_1x (_mm512_roundscale_round_ph, __m512h, __m512h, 123, 8) +test_1x (_mm512_getmant_ph, __m512h, __m512h, 1, 1) +test_1y (_mm512_getmant_round_ph, __m512h, __m512h, 1, 1, 8) test_2 (_mm512_add_round_ph, __m512h, __m512h, __m512h, 8) test_2 (_mm512_sub_round_ph, __m512h, __m512h, __m512h, 8) test_2 (_mm512_mul_round_ph, __m512h, __m512h, __m512h, 8) @@ -789,9 +835,58 @@ test_2 (_mm_max_round_sh, __m128h, __m128h, __m128h, 8) test_2 (_mm_min_round_sh, __m128h, __m128h, __m128h, 8) test_2 (_mm512_cmp_ph_mask, __mmask32, __m512h, __m512h, 1) test_2 (_mm_comi_sh, int, __m128h, __m128h, 1) +test_2 (_mm512_maskz_sqrt_round_ph, __m512h, __mmask32, __m512h, 8) +test_2 (_mm_sqrt_round_sh, __m128h, __m128h, __m128h, 8) +test_2 (_mm512_scalef_round_ph, __m512h, __m512h, __m512h, 8) +test_2 (_mm_maskz_reduce_ph, __m128h, __mmask8, __m128h, 123) +test_2 (_mm256_maskz_reduce_ph, __m256h, __mmask16, __m256h, 123) +test_2 (_mm512_maskz_reduce_ph, __m512h, __mmask32, __m512h, 123) +test_2 (_mm_reduce_sh, __m128h, __m128h, __m128h, 123) +test_2 (_mm_maskz_roundscale_ph, __m128h, __mmask8, __m128h, 123) +test_2 (_mm256_maskz_roundscale_ph, __m256h, __mmask16, __m256h, 123) +test_2 (_mm512_maskz_roundscale_ph, __m512h, __mmask32, __m512h, 123) +test_2 (_mm_roundscale_sh, __m128h, __m128h, __m128h, 123) +test_2 (_mm512_maskz_getexp_round_ph, __m512h, __mmask32, __m512h, 8) +test_2 (_mm_getexp_round_sh, __m128h, __m128h, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu16, __m512i, __mmask32, __m512h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvt_roundph_epi64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_epu64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu32, __m512i, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epi64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundph_pd, __m512d, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvtx_roundph_ps, __m512, __mmask16, __m256h, 8) +test_2 (_mm512_maskz_cvtt_roundph_epu64, __m512i, __mmask8, __m128h, 8) +test_2 (_mm512_maskz_cvt_roundepi16_ph, __m512h, __mmask32, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu16_ph, __m512h, __mmask32, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepi32_ph, __m256h, __mmask16, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu32_ph, __m256h, __mmask16, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepi64_ph, __m128h, __mmask8, __m512i, 8) +test_2 (_mm512_maskz_cvt_roundepu64_ph, __m128h, __mmask8, __m512i, 8) +test_2 (_mm512_maskz_cvtx_roundps_ph, __m256h, __mmask16, __m512, 8) +test_2 (_mm512_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m512d, 8) +test_2 (_mm_cvt_roundi32_sh, __m128h, __m128h, int, 8) +test_2 (_mm_cvt_roundu32_sh, __m128h, __m128h, unsigned, 8) +test_2 (_mm_cvt_roundsh_ss, __m128, __m128, __m128h, 8) +test_2 (_mm_cvt_roundsh_sd, __m128d, __m128d, __m128h, 8) +test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8) +test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8) test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8) test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8) test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8) +test_2x (_mm512_maskz_reduce_round_ph, __m512h, __mmask32, __m512h, 123, 8) +test_2x (_mm512_maskz_roundscale_round_ph, __m512h, __mmask32, __m512h, 123, 8) +test_2x (_mm_reduce_round_sh, __m128h, __m128h, __m128h, 123, 8) +test_2x (_mm_roundscale_round_sh, __m128h, __m128h, __m128h, 123, 8) +test_2x (_mm512_maskz_getmant_ph, __m512h, __mmask32, __m512h, 1, 1) +test_2x (_mm_getmant_sh, __m128h, __m128h, __m128h, 1, 1) +test_2y (_mm512_maskz_getmant_round_ph, __m512h, __mmask32, __m512h, 1, 1, 8) +test_2y (_mm_getmant_round_sh, __m128h, __m128h, __m128h, 1, 1, 8) test_3 (_mm512_maskz_add_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm512_maskz_sub_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm512_maskz_mul_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) @@ -805,8 +900,55 @@ test_3 (_mm512_maskz_min_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) test_3 (_mm_maskz_max_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) test_3 (_mm_maskz_min_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) test_3 (_mm512_mask_cmp_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1) +test_3 (_mm512_mask_sqrt_round_ph, __m512h, __m512h, __mmask32, __m512h, 8) +test_3 (_mm_maskz_sqrt_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) +test_3 (_mm512_maskz_scalef_round_ph, __m512h, __mmask32, __m512h, __m512h, 8) +test_3 (_mm_mask_reduce_ph, __m128h, __m128h, __mmask8, __m128h, 123) +test_3 (_mm256_mask_reduce_ph, __m256h, __m256h, __mmask16, __m256h, 123) +test_3 (_mm512_mask_reduce_ph, __m512h, __m512h, __mmask32, __m512h, 123) +test_3 (_mm_maskz_reduce_sh, __m128h, __mmask8, __m128h, __m128h, 123) +test_3 (_mm_mask_roundscale_ph, __m128h, __m128h, __mmask8, __m128h, 123) +test_3 (_mm256_mask_roundscale_ph, __m256h, __m256h, __mmask16, __m256h, 123) +test_3 (_mm512_mask_roundscale_ph, __m512h, __m512h, __mmask32, __m512h, 123) +test_3 (_mm_maskz_roundscale_sh, __m128h, __mmask8, __m128h, __m128h, 123) +test_3 (_mm_maskz_getexp_round_sh, __m128h, __mmask8, __m128h, __m128h, 8) +test_3 (_mm512_mask_getexp_round_ph, __m512h, __m512h, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epi16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epu16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu16, __m512i, __m512i, __mmask32, __m512h, 8) +test_3 (_mm512_mask_cvt_roundph_epi32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvt_roundph_epu32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvt_roundph_epi64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundph_epu64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu32, __m512i, __m512i, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epi64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundph_pd, __m512d, __m512d, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvtx_roundph_ps, __m512, __m512, __mmask16, __m256h, 8) +test_3 (_mm512_mask_cvtt_roundph_epu64, __m512i, __m512i, __mmask8, __m128h, 8) +test_3 (_mm512_mask_cvt_roundepi16_ph, __m512h, __m512h, __mmask32, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu16_ph, __m512h, __m512h, __mmask32, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepi32_ph, __m256h, __m256h, __mmask16, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu32_ph, __m256h, __m256h, __mmask16, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepi64_ph, __m128h, __m128h, __mmask8, __m512i, 8) +test_3 (_mm512_mask_cvt_roundepu64_ph, __m128h, __m128h, __mmask8, __m512i, 8) +test_3 (_mm512_mask_cvtx_roundps_ph, __m256h, __m256h, __mmask16, __m512, 8) +test_3 (_mm512_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m512d, 8) +test_3 (_mm_maskz_cvt_roundsh_ss, __m128, __mmask8, __m128, __m128h, 8) +test_3 (_mm_maskz_cvt_roundsh_sd, __m128d, __mmask8, __m128d, __m128h, 8) +test_3 (_mm_maskz_cvt_roundss_sh, __m128h, __mmask8, __m128h, __m128, 8) +test_3 (_mm_maskz_cvt_roundsd_sh, __m128h, __mmask8, __m128h, __m128d, 8) test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8) test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8) +test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) +test_3x (_mm512_mask_roundscale_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) +test_3x (_mm_maskz_reduce_round_sh, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_3x (_mm_maskz_roundscale_round_sh, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_3x (_mm512_mask_getmant_ph, __m512h, __m512h, __mmask32, __m512h, 1, 1) +test_3x (_mm_maskz_getmant_sh, __m128h, __mmask8, __m128h, __m128h, 1, 1) +test_3y (_mm_maskz_getmant_round_sh, __m128h, __mmask8, __m128h, __m128h, 1, 1, 8) +test_3y (_mm512_mask_getmant_round_ph, __m512h, __m512h, __mmask32, __m512h, 1, 1, 8) test_4 (_mm512_mask_add_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm512_mask_sub_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm512_mask_mul_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) @@ -819,6 +961,19 @@ test_4 (_mm512_mask_max_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, test_4 (_mm512_mask_min_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) test_4 (_mm_mask_max_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) test_4 (_mm_mask_min_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm_mask_sqrt_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm512_mask_scalef_round_ph, __m512h, __m512h, __mmask32, __m512h, __m512h, 8) +test_4 (_mm_mask_reduce_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123) +test_4 (_mm_mask_roundscale_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123) +test_4 (_mm_mask_getexp_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 8) +test_4 (_mm_mask_cvt_roundsh_ss, __m128, __m128, __mmask8, __m128, __m128h, 8) +test_4 (_mm_mask_cvt_roundsh_sd, __m128d, __m128d, __mmask8, __m128d, __m128h, 8) +test_4 (_mm_mask_cvt_roundss_sh, __m128h, __m128h, __mmask8, __m128h, __m128, 8) +test_4 (_mm_mask_cvt_roundsd_sh, __m128h, __m128h, __mmask8, __m128h, __m128d, 8) +test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) +test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1) +test_4y (_mm_mask_getmant_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1, 8) /* avx512fp16vlintrin.h */ test_2 (_mm_cmp_ph_mask, __mmask8, __m128h, __m128h, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index f6768ba..9c32b7b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -704,25 +704,85 @@ #define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E) /* avx512fp16intrin.h */ -#define __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vaddsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vsubsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmulsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vdivsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vminph_v32hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vmaxsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vminsh_v8hf_mask_round(A, B, C, D, 8) -#define __builtin_ia32_vcmpph_v32hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v32hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v32hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpph_v32hf_mask_round(A, B, 1, D, 8) -#define __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, C, D, E) __builtin_ia32_vcmpsh_v8hf_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_addph512_mask_round(A, B, C, D, E) __builtin_ia32_addph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subph512_mask_round(A, B, C, D, E) __builtin_ia32_subph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulph512_mask_round(A, B, C, D, E) __builtin_ia32_mulph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divph512_mask_round(A, B, C, D, E) __builtin_ia32_divph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_addsh_mask_round(A, B, C, D, E) __builtin_ia32_addsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_subsh_mask_round(A, B, C, D, E) __builtin_ia32_subsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_mulsh_mask_round(A, B, C, D, E) __builtin_ia32_mulsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_divsh_mask_round(A, B, C, D, E) __builtin_ia32_divsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxph512_mask_round(A, B, C, D, E) __builtin_ia32_maxph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minph512_mask_round(A, B, C, D, E) __builtin_ia32_minph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_maxsh_mask_round(A, B, C, D, E) __builtin_ia32_maxsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_minsh_mask_round(A, B, C, D, E) __builtin_ia32_minsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_cmpph512_mask(A, B, C, D) __builtin_ia32_cmpph512_mask(A, B, 1, D) +#define __builtin_ia32_cmpph512_mask_round(A, B, C, D, E) __builtin_ia32_cmpph512_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_cmpsh_mask_round(A, B, C, D, E) __builtin_ia32_cmpsh_mask_round(A, B, 1, D, 8) +#define __builtin_ia32_sqrtph512_mask_round(C, A, B, D) __builtin_ia32_sqrtph512_mask_round(C, A, B, 8) +#define __builtin_ia32_sqrtsh_mask_round(D, C, A, B, E) __builtin_ia32_sqrtsh_mask_round(D, C, A, B, 8) +#define __builtin_ia32_scalefph512_mask_round(A, B, C, D, E) __builtin_ia32_scalefph512_mask_round(A, B, C, D, 8) +#define __builtin_ia32_scalefsh_mask_round(A, B, C, D, E) __builtin_ia32_scalefsh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_reduceph512_mask_round(A, B, C, D, E) __builtin_ia32_reduceph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_reduceph128_mask(A, B, C, D) __builtin_ia32_reduceph128_mask(A, 123, C, D) +#define __builtin_ia32_reduceph256_mask(A, B, C, D) __builtin_ia32_reduceph256_mask(A, 123, C, D) +#define __builtin_ia32_reducesh_mask_round(A, B, C, D, E, F) __builtin_ia32_reducesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_rndscaleph512_mask_round(A, B, C, D, E) __builtin_ia32_rndscaleph512_mask_round(A, 123, C, D, 8) +#define __builtin_ia32_rndscaleph128_mask(A, B, C, D) __builtin_ia32_rndscaleph128_mask(A, 123, C, D) +#define __builtin_ia32_rndscaleph256_mask(A, B, C, D) __builtin_ia32_rndscaleph256_mask(A, 123, C, D) +#define __builtin_ia32_rndscalesh_mask_round(A, B, C, D, E, F) __builtin_ia32_rndscalesh_mask_round(A, B, 123, D, E, 8) +#define __builtin_ia32_fpclassph512_mask(A, D, C) __builtin_ia32_fpclassph512_mask(A, 1, C) +#define __builtin_ia32_fpclasssh_mask(A, D, U) __builtin_ia32_fpclasssh_mask(A, 1, U) +#define __builtin_ia32_getexpph512_mask(A, B, C, D) __builtin_ia32_getexpph512_mask(A, B, C, 8) +#define __builtin_ia32_getexpsh_mask_round(A, B, C, D, E) __builtin_ia32_getexpsh_mask_round(A, B, C, D, 4) +#define __builtin_ia32_getmantph512_mask(A, F, C, D, E) __builtin_ia32_getmantph512_mask(A, 1, C, D, 8) +#define __builtin_ia32_getmantsh_mask_round(A, B, C, W, U, D) __builtin_ia32_getmantsh_mask_round(A, B, 1, W, U, 4) +#define __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2dq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2udq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2qq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uqq512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2w512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2w512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, D) __builtin_ia32_vcvttph2uw512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuw2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtudq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtuqq2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2si32_round(A, B) __builtin_ia32_vcvtsh2si32_round(A, 8) +#define __builtin_ia32_vcvtsh2si64_round(A, B) __builtin_ia32_vcvtsh2si64_round(A, 8) +#define __builtin_ia32_vcvtsh2usi32_round(A, B) __builtin_ia32_vcvtsh2usi32_round(A, 8) +#define __builtin_ia32_vcvtsh2usi64_round(A, B) __builtin_ia32_vcvtsh2usi64_round(A, 8) +#define __builtin_ia32_vcvttsh2si32_round(A, B) __builtin_ia32_vcvttsh2si32_round(A, 8) +#define __builtin_ia32_vcvttsh2si64_round(A, B) __builtin_ia32_vcvttsh2si64_round(A, 8) +#define __builtin_ia32_vcvttsh2usi32_round(A, B) __builtin_ia32_vcvttsh2usi32_round(A, 8) +#define __builtin_ia32_vcvttsh2usi64_round(A, B) __builtin_ia32_vcvttsh2usi64_round(A, 8) +#define __builtin_ia32_vcvtsi2sh32_round(A, B, C) __builtin_ia32_vcvtsi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtsi2sh64_round(A, B, C) __builtin_ia32_vcvtsi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh32_round(A, B, C) __builtin_ia32_vcvtusi2sh32_round(A, B, 8) +#define __builtin_ia32_vcvtusi2sh64_round(A, B, C) __builtin_ia32_vcvtusi2sh64_round(A, B, 8) +#define __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2pd512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, D) __builtin_ia32_vcvtph2psx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx512_mask_round(A, B, C, 8) +#define __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2ss_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsh2sd_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtss2sh_mask_round(A, B, C, D, 8) +#define __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, E) __builtin_ia32_vcvtsd2sh_mask_round(A, B, C, D, 8) /* avx512fp16vlintrin.h */ -#define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D) -#define __builtin_ia32_vcmpph_v16hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v16hf_mask(A, B, 1, D) +#define __builtin_ia32_cmpph128_mask(A, B, C, D) __builtin_ia32_cmpph128_mask(A, B, 1, D) +#define __builtin_ia32_cmpph256_mask(A, B, C, D) __builtin_ia32_cmpph256_mask(A, B, 1, D) +#define __builtin_ia32_fpclassph256_mask(A, D, C) __builtin_ia32_fpclassph256_mask(A, 1, C) +#define __builtin_ia32_fpclassph128_mask(A, D, C) __builtin_ia32_fpclassph128_mask(A, 1, C) +#define __builtin_ia32_getmantph256_mask(A, E, C, D) __builtin_ia32_getmantph256_mask(A, 1, C, D) +#define __builtin_ia32_getmantph128_mask(A, E, C, D) __builtin_ia32_getmantph128_mask(A, 1, C, D) /* vpclmulqdqintrin.h */ #define __builtin_ia32_vpclmulqdq_v4di(A, B, C) __builtin_ia32_vpclmulqdq_v4di(A, B, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-covert-1.c new file mode 100644 index 0000000..c30af69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-covert-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency,^sse_partial_reg_converts_dependency" } */ + +extern float f; +extern double d; +extern int i; + +void +foo (void) +{ + d = f; + f = i; +} + +/* { dg-final { scan-assembler "cvtss2sd" } } */ +/* { dg-final { scan-assembler "cvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "cvtps2pd" } } */ +/* { dg-final { scan-assembler-not "cvtdq2ps" } } */ +/* { dg-final { scan-assembler-not "pxor" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c new file mode 100644 index 0000000..b6567e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency" } */ + +extern float f; +extern double d; + +void +foo (void) +{ + d = f; +} + +/* { dg-final { scan-assembler "cvtss2sd" } } */ +/* { dg-final { scan-assembler-not "cvtps2pd" } } */ +/* { dg-final { scan-assembler-not "pxor" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c new file mode 100644 index 0000000..107f724 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_converts_dependency" } */ + +extern float f; +extern int i; + +void +foo (void) +{ + f = i; +} + +/* { dg-final { scan-assembler "cvtsi2ssl" } } */ +/* { dg-final { scan-assembler-not "pxor" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c index 0c65172..715b281 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c @@ -5,14 +5,16 @@ void foo (__vector_quad *dst) { - __vector_quad acc; - __builtin_mma_xxsetaccz (&acc); - *dst = acc; + __vector_quad acc0, acc1; + __builtin_mma_xxsetaccz (&acc0); + __builtin_mma_xxsetaccz (&acc1); + dst[0] = acc0; + dst[1] = acc1; } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ /* { dg-final { scan-assembler-not {\mlxvp\M} } } */ /* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */ -/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mxxmfacc\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/20210917-1.c b/gcc/testsuite/gcc.target/sparc/20210917-1.c new file mode 100644 index 0000000..03e8bc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20210917-1.c @@ -0,0 +1,19 @@ +/* PR rtl-optimization/102306 */ +/* Reported by Daniel Cederman <cederman@gaisler.com> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O -mcpu=v8" } */ + +extern void foo (void); + +void test (volatile unsigned char *a) +{ + char b = *a; + if (!b) + return; + if (b & 2) + foo (); +} + +/* { dg-final { scan-assembler-times "ldub" 1 } } */ diff --git a/gcc/testsuite/gfortran.dg/PR100914.c b/gcc/testsuite/gfortran.dg/PR100914.c index c6bd973..ea339e7 100644 --- a/gcc/testsuite/gfortran.dg/PR100914.c +++ b/gcc/testsuite/gfortran.dg/PR100914.c @@ -5,7 +5,6 @@ #include <stdbool.h> #include <stdio.h> #include <math.h> -#include <quadmath.h> #include <ISO_Fortran_binding.h> @@ -29,7 +28,7 @@ #define CMPLXL(x, y) ((long double complex)((long double)(x) + (long double complex)I * (long double)(y))) #undef CMPLX -#define CMPLX(x, y) ((__complex128 )((double)(x) + (double complex)I * (double)(y))) +#define CMPLX(x, y) ((_Float128 _Complex )((double)(x) + (double complex)I * (double)(y))) #define N 11 #define M 7 @@ -37,7 +36,7 @@ typedef float _Complex c_float_complex; typedef double _Complex c_double_complex; typedef long double _Complex c_long_double_complex; -typedef __complex128 c_float128_complex; +typedef _Float128 _Complex c_float128_complex; bool c_vrfy_c_float_complex (const CFI_cdesc_t *restrict); diff --git a/gcc/testsuite/gfortran.dg/PR100914.f90 b/gcc/testsuite/gfortran.dg/PR100914.f90 index 64b3335..d8057fd 100644 --- a/gcc/testsuite/gfortran.dg/PR100914.f90 +++ b/gcc/testsuite/gfortran.dg/PR100914.f90 @@ -2,6 +2,7 @@ ! { dg-do run { xfail { { x86_64*-*-* i?86*-*-* } && longdouble128 } } } ! { dg-additional-sources PR100914.c } ! { dg-require-effective-target fortran_real_c_float128 } +! { dg-additional-options "-Wno-pedantic" } ! ! Test the fix for PR100914 ! diff --git a/gcc/testsuite/gfortran.dg/c-interop/typecodes-array-float128-c.c b/gcc/testsuite/gfortran.dg/c-interop/typecodes-array-float128-c.c index d081feb..4fcb6e2 100644 --- a/gcc/testsuite/gfortran.dg/c-interop/typecodes-array-float128-c.c +++ b/gcc/testsuite/gfortran.dg/c-interop/typecodes-array-float128-c.c @@ -32,7 +32,7 @@ void ctest (CFI_cdesc_t *arg_float128, CFI_cdesc_t *arg_complex128) { - check (arg_float128, sizeof (__float128), CFI_type_float128); - check (arg_complex128, sizeof (__float128) * 2, + check (arg_float128, sizeof (_Float128), CFI_type_float128); + check (arg_complex128, sizeof (_Float128) * 2, CFI_type_float128_Complex); } diff --git a/gcc/testsuite/gfortran.dg/c-interop/typecodes-sanity-c.c b/gcc/testsuite/gfortran.dg/c-interop/typecodes-sanity-c.c index a1d044b..90f0b20 100644 --- a/gcc/testsuite/gfortran.dg/c-interop/typecodes-sanity-c.c +++ b/gcc/testsuite/gfortran.dg/c-interop/typecodes-sanity-c.c @@ -23,8 +23,7 @@ static struct tc_info tc_table[] = { /* Extension types. Note there is no portable C equivalent type for CFI_type_ucs4_char type - (4-byte Unicode characters), and GCC rejects "__float128 _Complex", - so this is kind of hacky... */ + (4-byte Unicode characters), so this is kind of hacky... */ #if CFI_type_int128_t > 0 { CFI_type_int128_t, "CFI_type_int128_t", sizeof (__int128), 1 }, @@ -38,9 +37,9 @@ static struct tc_info tc_table[] = #endif #if CFI_type_float128 > 0 { CFI_type_float128, "CFI_type_float128", - sizeof (__float128), 1 }, + sizeof (_Float128), 1 }, { CFI_type_float128_Complex, "CFI_type_float128_Complex", - sizeof (__float128) * 2, 1 }, + sizeof (_Float128 _Complex), 1 }, #endif #if CFI_type_cfunptr > 0 { CFI_type_cfunptr, "CFI_type_cfunptr", diff --git a/gcc/testsuite/gfortran.dg/c-interop/typecodes-scalar-float128-c.c b/gcc/testsuite/gfortran.dg/c-interop/typecodes-scalar-float128-c.c index f1833aa..7eafa93 100644 --- a/gcc/testsuite/gfortran.dg/c-interop/typecodes-scalar-float128-c.c +++ b/gcc/testsuite/gfortran.dg/c-interop/typecodes-scalar-float128-c.c @@ -31,8 +31,8 @@ void ctest (CFI_cdesc_t *arg_float128, CFI_cdesc_t *arg_complex128) { - check (arg_float128, sizeof (__float128), CFI_type_float128); - check (arg_complex128, sizeof (__float128) * 2, + check (arg_float128, sizeof (_Float128), CFI_type_float128); + check (arg_complex128, sizeof (_Float128) * 2, CFI_type_float128_Complex); } diff --git a/gcc/testsuite/gfortran.dg/entry_25.f90 b/gcc/testsuite/gfortran.dg/entry_25.f90 new file mode 100644 index 0000000..518560a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/entry_25.f90 @@ -0,0 +1,13 @@ +! { dg-do compile } +! PR fortran/102311 - ICE during error recovery checking entry characteristics + +module m +contains + function f() ! { dg-error "mismatched characteristics" } + character(:), allocatable :: f + character(1) :: g + f = 'f' + entry g() + g = 'g' + end +end diff --git a/gcc/testsuite/gfortran.dg/goacc/unexpected-end.f90 b/gcc/testsuite/gfortran.dg/goacc/unexpected-end.f90 new file mode 100644 index 0000000..e9db47b --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/unexpected-end.f90 @@ -0,0 +1,25 @@ +! PR fortran/102313 + +!$acc end ATOMIC ! { dg-error "Unexpected !.ACC END ATOMIC" } + +!$acc end DATA ! { dg-error "Unexpected !.ACC END DATA" } + +!$acc end HOST_DATA ! { dg-error "Unexpected !.ACC END HOST_DATA" } + +!$acc end KERNELS ! { dg-error "Unexpected !.ACC END KERNELS" } + +!$acc end KERNELS LOOP ! { dg-error "Unexpected !.ACC END KERNELS LOOP" } + +!$acc end LOOP ! { dg-error "Unexpected !.ACC END LOOP" } + +!$acc end PARALLEL ! { dg-error "Unexpected !.ACC END PARALLEL" } + +!$acc end PARALLEL LOOP ! { dg-error "Unexpected !.ACC END PARALLEL LOOP" } + +!$acc end SERIAL ! { dg-error "Unexpected !.ACC END SERIAL" } + +!$acc end SERIAL LOOP ! { dg-error "Unexpected !.ACC END SERIAL LOOP" } + +!$acc end EUPHORBIA LATHYRIS ! { dg-error "Unclassifiable OpenACC directive" } + +end diff --git a/gcc/testsuite/gfortran.dg/gomp/unexpected-end.f90 b/gcc/testsuite/gfortran.dg/gomp/unexpected-end.f90 new file mode 100644 index 0000000..d2e8daa --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/unexpected-end.f90 @@ -0,0 +1,123 @@ +! PR fortran/102313 + +!$omp end ATOMIC ! { dg-error "Unexpected !.OMP END ATOMIC" } + +!$omp end CRITICAL ! { dg-error "Unexpected !.OMP END CRITICAL" } + +!$omp end DISTRIBUTE ! { dg-error "Unexpected !.OMP END DISTRIBUTE" } + +!$omp end DISTRIBUTE PARALLEL DO ! { dg-error "Unexpected !.OMP END DISTRIBUTE PARALLEL DO" } + +!$omp end DISTRIBUTE PARALLEL DO SIMD ! { dg-error "Unexpected !.OMP END DISTRIBUTE PARALLEL DO SIMD" } + +!$omp end DISTRIBUTE SIMD ! { dg-error "Unexpected !.OMP END DISTRIBUTE SIMD" } + +!$omp end DO ! { dg-error "Unexpected !.OMP END DO" } + +!$omp end DO SIMD ! { dg-error "Unexpected !.OMP END DO SIMD" } + +!$omp end LOOP ! { dg-error "Unclassifiable OpenMP directive" } + +!$omp parallel loop +do i = 1, 5 +end do +!$omp end LOOP ! { dg-error "Unclassifiable OpenMP directive" } + +!$omp end MASKED ! { dg-error "Unexpected !.OMP END MASKED" } + +!$omp end MASKED TASKLOOP ! { dg-error "Unexpected !.OMP END MASKED TASKLOOP" } + +!$omp end MASKED TASKLOOP SIMD ! { dg-error "Unexpected !.OMP END MASKED TASKLOOP SIMD" } + +!$omp end MASTER ! { dg-error "Unexpected !.OMP END MASTER" } + +!$omp end MASTER TASKLOOP ! { dg-error "Unexpected !.OMP END MASTER TASKLOOP" } + +!$omp end MASTER TASKLOOP SIMD ! { dg-error "Unexpected !.OMP END MASTER TASKLOOP SIMD" } + +!$omp end ORDERED ! { dg-error "Unexpected !.OMP END ORDERED" } + +!$omp end PARALLEL ! { dg-error "Unexpected !.OMP END PARALLEL" } + +!$omp end PARALLEL DO ! { dg-error "Unexpected !.OMP END PARALLEL DO" } + +!$omp end PARALLEL DO SIMD ! { dg-error "Unexpected !.OMP END PARALLEL DO SIMD" } + +!$omp loop +!$omp end PARALLEL LOOP ! { dg-error "Unexpected junk" } + +!$omp end PARALLEL MASKED ! { dg-error "Unexpected !.OMP END PARALLEL MASKED" } + +!$omp end PARALLEL MASKED TASKLOOP ! { dg-error "Unexpected !.OMP END PARALLEL MASKED TASKLOOP" } + +!$omp end PARALLEL MASKED TASKLOOP SIMD ! { dg-error "Unexpected !.OMP END PARALLEL MASKED TASKLOOP SIMD" } + +!$omp end PARALLEL MASTER ! { dg-error "Unexpected !.OMP END PARALLEL MASTER" } + +!$omp end PARALLEL MASTER TASKLOOP ! { dg-error "Unexpected !.OMP END PARALLEL MASTER TASKLOOP" } + +!$omp end PARALLEL MASTER TASKLOOP SIMD ! { dg-error "Unexpected !.OMP END PARALLEL MASTER TASKLOOP SIMD" } + +!$omp end PARALLEL SECTIONS ! { dg-error "Unexpected !.OMP END PARALLEL SECTIONS" } + +!$omp end PARALLEL WORKSHARE ! { dg-error "Unexpected !.OMP END PARALLEL WORKSHARE" } + +!$omp end SCOPE ! { dg-error "Unexpected !.OMP END SCOPE" } + +!$omp end SECTIONS ! { dg-error "Unexpected !.OMP END SECTIONS" } + +!$omp end SIMD ! { dg-error "Unexpected !.OMP END SIMD" } + +!$omp end SINGLE ! { dg-error "Unexpected !.OMP END SINGLE" } + +!$omp end TARGET ! { dg-error "Unexpected !.OMP END TARGET" } + +!$omp end TARGET DATA ! { dg-error "Unexpected !.OMP END TARGET DATA" } + +!$omp end TARGET PARALLEL ! { dg-error "Unexpected !.OMP END TARGET PARALLEL" } + +!$omp end TARGET PARALLEL DO ! { dg-error "Unexpected !.OMP END TARGET PARALLEL DO" } + +!$omp end TARGET PARALLEL DO SIMD ! { dg-error "Unexpected !.OMP END TARGET PARALLEL DO SIMD" } + +!$omp end TARGET PARALLEL LOOP ! { dg-error "Unexpected junk" } + +!$omp end TARGET SIMD ! { dg-error "Unexpected !.OMP END TARGET SIMD" } + +!$omp end TARGET TEAMS ! { dg-error "Unexpected !.OMP END TARGET TEAMS" } + +!$omp end TARGET TEAMS DISTRIBUTE ! { dg-error "Unexpected !.OMP END TARGET TEAMS DISTRIBUTE" } + +!$omp end TARGET TEAMS DISTRIBUTE PARALLEL DO ! { dg-error "Unexpected !.OMP END TARGET TEAMS DISTRIBUTE PARALLEL DO" } + +!$omp end TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD ! { dg-error "Unexpected !.OMP END TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD" } + +!$omp end TARGET TEAMS DISTRIBUTE SIMD ! { dg-error "Unexpected !.OMP END TARGET TEAMS DISTRIBUTE SIMD" } + +!$omp end TARGET TEAMS LOOP ! { dg-error "Unexpected junk" } + +!$omp end TASK ! { dg-error "Unexpected !.OMP END TASK" } + +!$omp end TASKGROUP ! { dg-error "Unexpected !.OMP END TASKGROUP" } + +!$omp end TASKLOOP ! { dg-error "Unexpected !.OMP END TASKLOOP" } + +!$omp end TASKLOOP SIMD ! { dg-error "Unexpected !.OMP END TASKLOOP SIMD" } + +!$omp end TEAMS ! { dg-error "Unexpected !.OMP END TEAMS" } + +!$omp end TEAMS DISTRIBUTE ! { dg-error "Unexpected !.OMP END TEAMS DISTRIBUTE" } + +!$omp end TEAMS DISTRIBUTE PARALLEL DO ! { dg-error "Unexpected !.OMP END TEAMS DISTRIBUTE PARALLEL DO" } + +!$omp end TEAMS DISTRIBUTE PARALLEL DO SIMD ! { dg-error "Unexpected !.OMP END TEAMS DISTRIBUTE PARALLEL DO SIMD" } + +!$omp end TEAMS DISTRIBUTE SIMD ! { dg-error "Unexpected !.OMP END TEAMS DISTRIBUTE SIMD" } + +!$omp end TEAMS LOOP ! { dg-error "Unexpected junk" } + +!$omp end WORKSHARE ! { dg-error "Unexpected !.OMP END WORKSHARE" } + +end ! { dg-error "Unexpected END statement" } + +! { dg-excess-errors "Unexpected end of file" } diff --git a/gcc/testsuite/gfortran.dg/intent_out_14.f90 b/gcc/testsuite/gfortran.dg/intent_out_14.f90 new file mode 100644 index 0000000..e599463 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/intent_out_14.f90 @@ -0,0 +1,24 @@ +! { dg-do run } +! PR fortran/102287 - optional allocatable DT array arguments (intent out) + +module m + type t + integer, allocatable :: a + end type t +contains + subroutine a (x, v) + type(t), optional, allocatable, intent(out) :: x(:) + type(t), optional, intent(out) :: v(:) + call b (x, v) + end subroutine a + + subroutine b (y, w) + type(t), optional, allocatable, intent(out) :: y(:) + type(t), optional, intent(out) :: w(:) + end subroutine b +end module m + +program p + use m + call a () +end diff --git a/gcc/testsuite/gnat.dg/enum_rep2.adb b/gcc/testsuite/gnat.dg/enum_rep2.adb new file mode 100644 index 0000000..6554ad4 --- /dev/null +++ b/gcc/testsuite/gnat.dg/enum_rep2.adb @@ -0,0 +1,117 @@ +-- { dg-do compile } + +with Ada.Integer_Text_IO; +with Ada.Text_IO; + +procedure Enum_Rep2 is + + type T is + (E80, E81, E82, E83, E84, E85, E86, E87, E88, E89, E8A, E8B, E8C, E8D, E8E, E8F, + E90, E91, E92, E93, E94, E95, E96, E97, E98, E99, E9A, E9B, E9C, E9D, E9E, E9F, + EA0, EA1, EA2, EA3, EA4, EA5, EA6, EA7, EA8, EA9, EAA, EAB, EAC, EAD, EAE, EAF, + EB0, EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EBA, EBB, EBC, EBD, EBE, EBF, + EC0, EC1, EC2, EC3, EC4, EC5, EC6, EC7, EC8, EC9, ECA, ECB, ECC, ECD, ECE, ECF, + ED0, ED1, ED2, ED3, ED4, ED5, ED6, ED7, ED8, ED9, EDA, EDB, EDC, EDD, EDE, EDF, + EE0, EE1, EE2, EE3, EE4, EE5, EE6, EE7, EE8, EE9, EEA, EEB, EEC, EED, EEE, EEF, + EF0, EF1, EF2, EF3, EF4, EF5, EF6, EF7, EF8, EF9, EFA, EFB, EFC, EFD, EFE, EFF, + E00, E01, E02, E03, E04, E05, E06, E07, E08, E09, E0A, E0B, E0C, E0D, E0E, E0F, + E10, E11, E12, E13, E14, E15, E16, E17, E18, E19, E1A, E1B, E1C, E1D, E1E, E1F, + E20, E21, E22, E23, E24, E25, E26, E27, E28, E29, E2A, E2B, E2C, E2D, E2E, E2F, + E30, E31, E32, E33, E34, E35, E36, E37, E38, E39, E3A, E3B, E3C, E3D, E3E, E3F, + E40, E41, E42, E43, E44, E45, E46, E47, E48, E49, E4A, E4B, E4C, E4D, E4E, E4F, + E50, E51, E52, E53, E54, E55, E56, E57, E58, E59, E5A, E5B, E5C, E5D, E5E, E5F, + E60, E61, E62, E63, E64, E65, E66, E67, E68, E69, E6A, E6B, E6C, E6D, E6E, E6F, + E70, E71, E72, E73, E74, E75, E76, E77, E78, E79, E7A, E7B, E7C, E7D, E7E, E7F); + for T use + (E80 => -16#80#, E81 => -16#7F#, E82 => -16#7E#, E83 => -16#7D#, + E84 => -16#7C#, E85 => -16#7B#, E86 => -16#7A#, E87 => -16#79#, + E88 => -16#78#, E89 => -16#77#, E8A => -16#76#, E8B => -16#75#, + E8C => -16#74#, E8D => -16#73#, E8E => -16#72#, E8F => -16#71#, + + E90 => -16#70#, E91 => -16#6F#, E92 => -16#6E#, E93 => -16#6D#, + E94 => -16#6C#, E95 => -16#6B#, E96 => -16#6A#, E97 => -16#69#, + E98 => -16#68#, E99 => -16#67#, E9A => -16#66#, E9B => -16#65#, + E9C => -16#64#, E9D => -16#63#, E9E => -16#62#, E9F => -16#61#, + + EA0 => -16#60#, EA1 => -16#5F#, EA2 => -16#5E#, EA3 => -16#5D#, + EA4 => -16#5C#, EA5 => -16#5B#, EA6 => -16#5A#, EA7 => -16#59#, + EA8 => -16#58#, EA9 => -16#57#, EAA => -16#56#, EAB => -16#55#, + EAC => -16#54#, EAD => -16#53#, EAE => -16#52#, EAF => -16#51#, + + EB0 => -16#50#, EB1 => -16#4F#, EB2 => -16#4E#, EB3 => -16#4D#, + EB4 => -16#4C#, EB5 => -16#4B#, EB6 => -16#4A#, EB7 => -16#49#, + EB8 => -16#48#, EB9 => -16#47#, EBA => -16#46#, EBB => -16#45#, + EBC => -16#44#, EBD => -16#43#, EBE => -16#42#, EBF => -16#41#, + + EC0 => -16#40#, EC1 => -16#3F#, EC2 => -16#3E#, EC3 => -16#3D#, + EC4 => -16#3C#, EC5 => -16#3B#, EC6 => -16#3A#, EC7 => -16#39#, + EC8 => -16#38#, EC9 => -16#37#, ECA => -16#36#, ECB => -16#35#, + ECC => -16#34#, ECD => -16#33#, ECE => -16#32#, ECF => -16#31#, + + ED0 => -16#30#, ED1 => -16#2F#, ED2 => -16#2E#, ED3 => -16#2D#, + ED4 => -16#2C#, ED5 => -16#2B#, ED6 => -16#2A#, ED7 => -16#29#, + ED8 => -16#28#, ED9 => -16#27#, EDA => -16#26#, EDB => -16#25#, + EDC => -16#24#, EDD => -16#23#, EDE => -16#22#, EDF => -16#21#, + + EE0 => -16#20#, EE1 => -16#1F#, EE2 => -16#1E#, EE3 => -16#1D#, + EE4 => -16#1C#, EE5 => -16#1B#, EE6 => -16#1A#, EE7 => -16#19#, + EE8 => -16#18#, EE9 => -16#17#, EEA => -16#16#, EEB => -16#15#, + EEC => -16#14#, EED => -16#13#, EEE => -16#12#, EEF => -16#11#, + + EF0 => -16#10#, EF1 => -16#0F#, EF2 => -16#0E#, EF3 => -16#0D#, + EF4 => -16#0C#, EF5 => -16#0B#, EF6 => -16#0A#, EF7 => -16#09#, + EF8 => -16#08#, EF9 => -16#07#, EFA => -16#06#, EFB => -16#05#, + EFC => -16#04#, EFD => -16#03#, EFE => -16#02#, EFF => -16#01#, + + E00 => 16#00#, E01 => 16#01#, E02 => 16#02#, E03 => 16#03#, + E04 => 16#04#, E05 => 16#05#, E06 => 16#06#, E07 => 16#07#, + E08 => 16#08#, E09 => 16#09#, E0A => 16#0A#, E0B => 16#0B#, + E0C => 16#0C#, E0D => 16#0D#, E0E => 16#0E#, E0F => 16#0F#, + + E10 => 16#10#, E11 => 16#11#, E12 => 16#12#, E13 => 16#13#, + E14 => 16#14#, E15 => 16#15#, E16 => 16#16#, E17 => 16#17#, + E18 => 16#18#, E19 => 16#19#, E1A => 16#1A#, E1B => 16#1B#, + E1C => 16#1C#, E1D => 16#1D#, E1E => 16#1E#, E1F => 16#1F#, + + E20 => 16#20#, E21 => 16#21#, E22 => 16#22#, E23 => 16#23#, + E24 => 16#24#, E25 => 16#25#, E26 => 16#26#, E27 => 16#27#, + E28 => 16#28#, E29 => 16#29#, E2A => 16#2A#, E2B => 16#2B#, + E2C => 16#2C#, E2D => 16#2D#, E2E => 16#2E#, E2F => 16#2F#, + + E30 => 16#30#, E31 => 16#31#, E32 => 16#32#, E33 => 16#33#, + E34 => 16#34#, E35 => 16#35#, E36 => 16#36#, E37 => 16#37#, + E38 => 16#38#, E39 => 16#39#, E3A => 16#3A#, E3B => 16#3B#, + E3C => 16#3C#, E3D => 16#3D#, E3E => 16#3E#, E3F => 16#3F#, + + E40 => 16#40#, E41 => 16#41#, E42 => 16#42#, E43 => 16#43#, + E44 => 16#44#, E45 => 16#45#, E46 => 16#46#, E47 => 16#47#, + E48 => 16#48#, E49 => 16#49#, E4A => 16#4A#, E4B => 16#4B#, + E4C => 16#4C#, E4D => 16#4D#, E4E => 16#4E#, E4F => 16#4F#, + + E50 => 16#50#, E51 => 16#51#, E52 => 16#52#, E53 => 16#53#, + E54 => 16#54#, E55 => 16#55#, E56 => 16#56#, E57 => 16#57#, + E58 => 16#58#, E59 => 16#59#, E5A => 16#5A#, E5B => 16#5B#, + E5C => 16#5C#, E5D => 16#5D#, E5E => 16#5E#, E5F => 16#5F#, + + E60 => 16#60#, E61 => 16#61#, E62 => 16#62#, E63 => 16#63#, + E64 => 16#64#, E65 => 16#65#, E66 => 16#66#, E67 => 16#67#, + E68 => 16#68#, E69 => 16#69#, E6A => 16#6A#, E6B => 16#6B#, + E6C => 16#6C#, E6D => 16#6D#, E6E => 16#6E#, E6F => 16#6F#, + + E70 => 16#70#, E71 => 16#71#, E72 => 16#72#, E73 => 16#73#, + E74 => 16#74#, E75 => 16#75#, E76 => 16#76#, E77 => 16#77#, + E78 => 16#78#, E79 => 16#79#, E7A => 16#7A#, E7B => 16#7B#, + E7C => 16#7C#, E7D => 16#7D#, E7E => 16#7E#, E7F => 16#7F#); + for T'Size use 8; + + procedure Print (X : T) is + begin + Ada.Integer_Text_IO.Put (T'Pos (X)); + Ada.Integer_Text_IO.Put (T'Enum_Rep (X)); + Ada.Text_IO.New_Line; + end; + +begin + Print (T'First); + Print (T'Last); +end; diff --git a/gcc/testsuite/gnat.dg/zcur_attr.adb b/gcc/testsuite/gnat.dg/zcur_attr.adb new file mode 100644 index 0000000..5d15f5e --- /dev/null +++ b/gcc/testsuite/gnat.dg/zcur_attr.adb @@ -0,0 +1,8 @@ +-- { dg-do compile } +-- { dg-options "-fdump-tree-optimized" } + +package body ZCUR_Attr is + function F return Integer is (0); +end ZCUR_Attr; + +-- { dg-final { scan-tree-dump "zero_call_used_regs \[(\]\"all\"\[)\]" "optimized" } } diff --git a/gcc/testsuite/gnat.dg/zcur_attr.ads b/gcc/testsuite/gnat.dg/zcur_attr.ads new file mode 100644 index 0000000..b756cc8 --- /dev/null +++ b/gcc/testsuite/gnat.dg/zcur_attr.ads @@ -0,0 +1,4 @@ +package ZCUR_Attr is + function F return Integer; + pragma Machine_Attribute (F, "zero_call_used_regs", "all"); +end ZCUR_Attr; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 82dc131..f11c4e6 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1578,8 +1578,8 @@ proc check_effective_target_fortran_real_10 { } { # Return 1 if the target supports Fortran real kind C_FLOAT128, # 0 otherwise. This differs from check_effective_target_fortran_real_16 -# because __float128 has the additional requirement that it be the -# 128-bit IEEE encoding; even if __float128 is available in C, it may not +# because _Float128 has the additional requirement that it be the +# 128-bit IEEE encoding; even if _Float128 is available in C, it may not # have a corresponding Fortran kind on targets (PowerPC) that use some # other encoding for long double/TFmode/real(16). proc check_effective_target_fortran_real_c_float128 { } { @@ -8074,7 +8074,7 @@ proc check_effective_target_sync_int_128_runtime { } { # Note: 32bit s390 targets require -mzarch in dg-options. proc check_effective_target_sync_long_long { } { - if { [istarget i?86-*-*] || [istarget x86_64-*-*]) + if { [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget aarch64*-*-*] || [istarget arm*-*-*] || [istarget alpha*-*-*] |