[ARM][GCC][4/4x]: MVE intrinsics with quaternary operands.

This patch supports following MVE ACLE intrinsics with quaternary operands.

vabdq_m_f32, vabdq_m_f16, vaddq_m_f32, vaddq_m_f16, vaddq_m_n_f32, vaddq_m_n_f16, vandq_m_f32, vandq_m_f16, vbicq_m_f32, vbicq_m_f16, vbrsrq_m_n_f32, vbrsrq_m_n_f16, vcaddq_rot270_m_f32, vcaddq_rot270_m_f16, vcaddq_rot90_m_f32, vcaddq_rot90_m_f16, vcmlaq_m_f32, vcmlaq_m_f16, vcmlaq_rot180_m_f32, vcmlaq_rot180_m_f16, vcmlaq_rot270_m_f32, vcmlaq_rot270_m_f16, vcmlaq_rot90_m_f32, vcmlaq_rot90_m_f16, vcmulq_m_f32, vcmulq_m_f16, vcmulq_rot180_m_f32, vcmulq_rot180_m_f16, vcmulq_rot270_m_f32, vcmulq_rot270_m_f16, vcmulq_rot90_m_f32, vcmulq_rot90_m_f16, vcvtq_m_n_s32_f32, vcvtq_m_n_s16_f16, vcvtq_m_n_u32_f32, vcvtq_m_n_u16_f16, veorq_m_f32, veorq_m_f16, vfmaq_m_f32, vfmaq_m_f16, vfmaq_m_n_f32, vfmaq_m_n_f16, vfmasq_m_n_f32, vfmasq_m_n_f16, vfmsq_m_f32, vfmsq_m_f16, vmaxnmq_m_f32, vmaxnmq_m_f16, vminnmq_m_f32, vminnmq_m_f16, vmulq_m_f32, vmulq_m_f16, vmulq_m_n_f32, vmulq_m_n_f16, vornq_m_f32, vornq_m_f16, vorrq_m_f32, vorrq_m_f16, vsubq_m_f32, vsubq_m_f16, vsubq_m_n_f32, vsubq_m_n_f16.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vabdq_m_f32): Define macro.
	(vabdq_m_f16): Likewise.
	(vaddq_m_f32): Likewise.
	(vaddq_m_f16): Likewise.
	(vaddq_m_n_f32): Likewise.
	(vaddq_m_n_f16): Likewise.
	(vandq_m_f32): Likewise.
	(vandq_m_f16): Likewise.
	(vbicq_m_f32): Likewise.
	(vbicq_m_f16): Likewise.
	(vbrsrq_m_n_f32): Likewise.
	(vbrsrq_m_n_f16): Likewise.
	(vcaddq_rot270_m_f32): Likewise.
	(vcaddq_rot270_m_f16): Likewise.
	(vcaddq_rot90_m_f32): Likewise.
	(vcaddq_rot90_m_f16): Likewise.
	(vcmlaq_m_f32): Likewise.
	(vcmlaq_m_f16): Likewise.
	(vcmlaq_rot180_m_f32): Likewise.
	(vcmlaq_rot180_m_f16): Likewise.
	(vcmlaq_rot270_m_f32): Likewise.
	(vcmlaq_rot270_m_f16): Likewise.
	(vcmlaq_rot90_m_f32): Likewise.
	(vcmlaq_rot90_m_f16): Likewise.
	(vcmulq_m_f32): Likewise.
	(vcmulq_m_f16): Likewise.
	(vcmulq_rot180_m_f32): Likewise.
	(vcmulq_rot180_m_f16): Likewise.
	(vcmulq_rot270_m_f32): Likewise.
	(vcmulq_rot270_m_f16): Likewise.
	(vcmulq_rot90_m_f32): Likewise.
	(vcmulq_rot90_m_f16): Likewise.
	(vcvtq_m_n_s32_f32): Likewise.
	(vcvtq_m_n_s16_f16): Likewise.
	(vcvtq_m_n_u32_f32): Likewise.
	(vcvtq_m_n_u16_f16): Likewise.
	(veorq_m_f32): Likewise.
	(veorq_m_f16): Likewise.
	(vfmaq_m_f32): Likewise.
	(vfmaq_m_f16): Likewise.
	(vfmaq_m_n_f32): Likewise.
	(vfmaq_m_n_f16): Likewise.
	(vfmasq_m_n_f32): Likewise.
	(vfmasq_m_n_f16): Likewise.
	(vfmsq_m_f32): Likewise.
	(vfmsq_m_f16): Likewise.
	(vmaxnmq_m_f32): Likewise.
	(vmaxnmq_m_f16): Likewise.
	(vminnmq_m_f32): Likewise.
	(vminnmq_m_f16): Likewise.
	(vmulq_m_f32): Likewise.
	(vmulq_m_f16): Likewise.
	(vmulq_m_n_f32): Likewise.
	(vmulq_m_n_f16): Likewise.
	(vornq_m_f32): Likewise.
	(vornq_m_f16): Likewise.
	(vorrq_m_f32): Likewise.
	(vorrq_m_f16): Likewise.
	(vsubq_m_f32): Likewise.
	(vsubq_m_f16): Likewise.
	(vsubq_m_n_f32): Likewise.
	(vsubq_m_n_f16): Likewise.
	(__attribute__): Likewise.
	(__arm_vabdq_m_f32): Likewise.
	(__arm_vabdq_m_f16): Likewise.
	(__arm_vaddq_m_f32): Likewise.
	(__arm_vaddq_m_f16): Likewise.
	(__arm_vaddq_m_n_f32): Likewise.
	(__arm_vaddq_m_n_f16): Likewise.
	(__arm_vandq_m_f32): Likewise.
	(__arm_vandq_m_f16): Likewise.
	(__arm_vbicq_m_f32): Likewise.
	(__arm_vbicq_m_f16): Likewise.
	(__arm_vbrsrq_m_n_f32): Likewise.
	(__arm_vbrsrq_m_n_f16): Likewise.
	(__arm_vcaddq_rot270_m_f32): Likewise.
	(__arm_vcaddq_rot270_m_f16): Likewise.
	(__arm_vcaddq_rot90_m_f32): Likewise.
	(__arm_vcaddq_rot90_m_f16): Likewise.
	(__arm_vcmlaq_m_f32): Likewise.
	(__arm_vcmlaq_m_f16): Likewise.
	(__arm_vcmlaq_rot180_m_f32): Likewise.
	(__arm_vcmlaq_rot180_m_f16): Likewise.
	(__arm_vcmlaq_rot270_m_f32): Likewise.
	(__arm_vcmlaq_rot270_m_f16): Likewise.
	(__arm_vcmlaq_rot90_m_f32): Likewise.
	(__arm_vcmlaq_rot90_m_f16): Likewise.
	(__arm_vcmulq_m_f32): Likewise.
	(__arm_vcmulq_m_f16): Likewise.
	(__arm_vcmulq_rot180_m_f32): Define intrinsic.
	(__arm_vcmulq_rot180_m_f16): Likewise.
	(__arm_vcmulq_rot270_m_f32): Likewise.
	(__arm_vcmulq_rot270_m_f16): Likewise.
	(__arm_vcmulq_rot90_m_f32): Likewise.
	(__arm_vcmulq_rot90_m_f16): Likewise.
	(__arm_vcvtq_m_n_s32_f32): Likewise.
	(__arm_vcvtq_m_n_s16_f16): Likewise.
	(__arm_vcvtq_m_n_u32_f32): Likewise.
	(__arm_vcvtq_m_n_u16_f16): Likewise.
	(__arm_veorq_m_f32): Likewise.
	(__arm_veorq_m_f16): Likewise.
	(__arm_vfmaq_m_f32): Likewise.
	(__arm_vfmaq_m_f16): Likewise.
	(__arm_vfmaq_m_n_f32): Likewise.
	(__arm_vfmaq_m_n_f16): Likewise.
	(__arm_vfmasq_m_n_f32): Likewise.
	(__arm_vfmasq_m_n_f16): Likewise.
	(__arm_vfmsq_m_f32): Likewise.
	(__arm_vfmsq_m_f16): Likewise.
	(__arm_vmaxnmq_m_f32): Likewise.
	(__arm_vmaxnmq_m_f16): Likewise.
	(__arm_vminnmq_m_f32): Likewise.
	(__arm_vminnmq_m_f16): Likewise.
	(__arm_vmulq_m_f32): Likewise.
	(__arm_vmulq_m_f16): Likewise.
	(__arm_vmulq_m_n_f32): Likewise.
	(__arm_vmulq_m_n_f16): Likewise.
	(__arm_vornq_m_f32): Likewise.
	(__arm_vornq_m_f16): Likewise.
	(__arm_vorrq_m_f32): Likewise.
	(__arm_vorrq_m_f16): Likewise.
	(__arm_vsubq_m_f32): Likewise.
	(__arm_vsubq_m_f16): Likewise.
	(__arm_vsubq_m_n_f32): Likewise.
	(__arm_vsubq_m_n_f16): Likewise.
	(vabdq_m): Define polymorphic variant.
	(vaddq_m): Likewise.
	(vaddq_m_n): Likewise.
	(vandq_m): Likewise.
	(vbicq_m): Likewise.
	(vbrsrq_m_n): Likewise.
	(vcaddq_rot270_m): Likewise.
	(vcaddq_rot90_m): Likewise.
	(vcmlaq_m): Likewise.
	(vcmlaq_rot180_m): Likewise.
	(vcmlaq_rot270_m): Likewise.
	(vcmlaq_rot90_m): Likewise.
	(vcmulq_m): Likewise.
	(vcmulq_rot180_m): Likewise.
	(vcmulq_rot270_m): Likewise.
	(vcmulq_rot90_m): Likewise.
	(veorq_m): Likewise.
	(vfmaq_m): Likewise.
	(vfmaq_m_n): Likewise.
	(vfmasq_m_n): Likewise.
	(vfmsq_m): Likewise.
	(vmaxnmq_m): Likewise.
	(vminnmq_m): Likewise.
	(vmulq_m): Likewise.
	(vmulq_m_n): Likewise.
	(vornq_m): Likewise.
	(vsubq_m): Likewise.
	(vsubq_m_n): Likewise.
	(vorrq_m): Likewise.
	* config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
	builtin qualifier.
	(QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
	* config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
	(mve_vaddq_m_f<mode>): Likewise.
	(mve_vaddq_m_n_f<mode>): Likewise.
	(mve_vandq_m_f<mode>): Likewise.
	(mve_vbicq_m_f<mode>): Likewise.
	(mve_vbrsrq_m_n_f<mode>): Likewise.
	(mve_vcaddq_rot270_m_f<mode>): Likewise.
	(mve_vcaddq_rot90_m_f<mode>): Likewise.
	(mve_vcmlaq_m_f<mode>): Likewise.
	(mve_vcmlaq_rot180_m_f<mode>): Likewise.
	(mve_vcmlaq_rot270_m_f<mode>): Likewise.
	(mve_vcmlaq_rot90_m_f<mode>): Likewise.
	(mve_vcmulq_m_f<mode>): Likewise.
	(mve_vcmulq_rot180_m_f<mode>): Likewise.
	(mve_vcmulq_rot270_m_f<mode>): Likewise.
	(mve_vcmulq_rot90_m_f<mode>): Likewise.
	(mve_veorq_m_f<mode>): Likewise.
	(mve_vfmaq_m_f<mode>): Likewise.
	(mve_vfmaq_m_n_f<mode>): Likewise.
	(mve_vfmasq_m_n_f<mode>): Likewise.
	(mve_vfmsq_m_f<mode>): Likewise.
	(mve_vmaxnmq_m_f<mode>): Likewise.
	(mve_vminnmq_m_f<mode>): Likewise.
	(mve_vmulq_m_f<mode>): Likewise.
	(mve_vmulq_m_n_f<mode>): Likewise.
	(mve_vornq_m_f<mode>): Likewise.
	(mve_vorrq_m_f<mode>): Likewise.
	(mve_vsubq_m_f<mode>): Likewise.
	(mve_vsubq_m_n_f<mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.

62 files changed, 1488 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
new file mode 100644
index 0000000..dac3dd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vabdq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
new file mode 100644
index 0000000..d1b59ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vabdq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vabdq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
new file mode 100644
index 0000000..b52b719
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vaddq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
new file mode 100644
index 0000000..c3e7c2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vaddq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
new file mode 100644
index 0000000..94d6b6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vaddq_m_n_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
new file mode 100644
index 0000000..ab100cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vaddq_m_n_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
new file mode 100644
index 0000000..c641fce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vandq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
new file mode 100644
index 0000000..a3344d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vandq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vandq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
new file mode 100644
index 0000000..f3237a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vbicq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
new file mode 100644
index 0000000..975d9db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vbicq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vbicq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
new file mode 100644
index 0000000..afb5ef8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
+{
+  return vbrsrq_m_n_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
+{
+  return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
new file mode 100644
index 0000000..3b612cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vbrsrq_m_n_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vbrsrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
new file mode 100644
index 0000000..52af15c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcaddq_rot270_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
new file mode 100644
index 0000000..b5fb2e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcaddq_rot270_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcaddq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
new file mode 100644
index 0000000..8db12c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcaddq_rot90_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
new file mode 100644
index 0000000..fae494c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcaddq_rot90_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcaddq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
new file mode 100644
index 0000000..3f86c8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
new file mode 100644
index 0000000..3cc3342
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
new file mode 100644
index 0000000..197d8ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot180_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot180_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
new file mode 100644
index 0000000..3bd195f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot180_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot180_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
new file mode 100644
index 0000000..29e8638
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot270_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot270_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
new file mode 100644
index 0000000..a4ca602
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot270_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot270_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
new file mode 100644
index 0000000..55afaf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot90_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot90_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
new file mode 100644
index 0000000..89be04b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot90_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vcmlaq_rot90_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
new file mode 100644
index 0000000..c83be6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
new file mode 100644
index 0000000..acea3b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
new file mode 100644
index 0000000..78e7606
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot180_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot180_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
new file mode 100644
index 0000000..8643de0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot180_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot180_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
new file mode 100644
index 0000000..632e21c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot270_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
new file mode 100644
index 0000000..e5f35de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot270_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot270_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
new file mode 100644
index 0000000..dfd5d0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot90_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vcmulq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
new file mode 100644
index 0000000..7b87791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot90_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vcmulq_rot90_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
new file mode 100644
index 0000000..62c3086
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n_s16_f16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
new file mode 100644
index 0000000..0eeba94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n_s32_f32 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
new file mode 100644
index 0000000..fbc3b9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n_u16_f16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
new file mode 100644
index 0000000..b7719de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n_u32_f32 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
new file mode 100644
index 0000000..8a70933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return veorq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
new file mode 100644
index 0000000..37ab556
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return veorq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return veorq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "veort"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
new file mode 100644
index 0000000..f27d664
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vfmaq_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vfmaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
new file mode 100644
index 0000000..7e7d38f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vfmaq_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vfmaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
new file mode 100644
index 0000000..93c8aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+{
+  return vfmaq_m_n_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+{
+  return vfmaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
new file mode 100644
index 0000000..1f9189a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+{
+  return vfmaq_m_n_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+{
+  return vfmaq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmat.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
new file mode 100644
index 0000000..4f91179
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+{
+  return vfmasq_m_n_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmast.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+{
+  return vfmasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmast.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
new file mode 100644
index 0000000..e630f44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+{
+  return vfmasq_m_n_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmast.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+{
+  return vfmasq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmast.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
new file mode 100644
index 0000000..2cda2e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vfmsq_m_f16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmst.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+{
+  return vfmsq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmst.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
new file mode 100644
index 0000000..773edf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vfmsq_m_f32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmst.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+{
+  return vfmsq_m (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vfmst.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
new file mode 100644
index 0000000..43858dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmaxnmq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
new file mode 100644
index 0000000..a3b7e8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmaxnmq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
new file mode 100644
index 0000000..d01e266
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vminnmq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
new file mode 100644
index 0000000..5193b2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vminnmq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
new file mode 100644
index 0000000..43b751b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmulq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
new file mode 100644
index 0000000..6dee764
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmulq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
new file mode 100644
index 0000000..a0b2d53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vmulq_m_n_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
new file mode 100644
index 0000000..c457195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vmulq_m_n_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmult.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
new file mode 100644
index 0000000..9833268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vornq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
new file mode 100644
index 0000000..48a720a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vornq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vornq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vornt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
new file mode 100644
index 0000000..6e8591e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vorrq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
new file mode 100644
index 0000000..09ee673
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vorrq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vorrq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vorrt"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
new file mode 100644
index 0000000..383491d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vsubq_m_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
new file mode 100644
index 0000000..327b524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vsubq_m_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
new file mode 100644
index 0000000..5657c36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vsubq_m_n_f16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+
+float16x8_t
+foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
new file mode 100644
index 0000000..c9502cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vsubq_m_n_f32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+
+float32x4_t
+foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vsubt.f32"  }  } */