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| author | Jackson Woodruff <jackson.woodruff@arm.com> | 2017-08-17 12:54:10 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2017-08-17 12:54:10 +0000 |
| commit | ea58eb88d9b440773e146bd6cb39abb9a9fb894f (patch) | |
| tree | 8729a6dc4aabe8ec96b44681dc1cb6dc1f1ddbc5 /gcc/testsuite/gcc.target | |
| parent | 0fc81d78f9e97d0fb9b7a6c051189758b1d2ab01 (diff) | |
| download | gcc-ea58eb88d9b440773e146bd6cb39abb9a9fb894f.zip gcc-ea58eb88d9b440773e146bd6cb39abb9a9fb894f.tar.gz gcc-ea58eb88d9b440773e146bd6cb39abb9a9fb894f.tar.bz2 | |
[AArch64] Improve SIMD store of zero.
This patch changes patterns in aarch64-simd.md to replace
movi v0.4s, 0
str q0, [x0, 16]
With:
stp xzr, xzr, [x0, 16]
When we are storing zeros to vectors like this:
void f(uint32x4_t *p) {
uint32x4_t x = { 0, 0, 0, 0};
p[1] = x;
}
gcc/
2017-08-17 Jackson Woodruff <jackson.woodruff@arm.com>
* aarch64-simd.md (mov<mode>): No longer force zero immediate into
register.
(*aarch64_simd_mov<mode>): Add new case for stp using zero immediate.
gcc/testsuite/
2017-08-17 Jackson Woodruff <jackson.woodruff@arm.com>
* gcc.target/aarch64/simd/vect_str_zero.c: New testcase.
From-SVN: r251149
Diffstat (limited to 'gcc/testsuite/gcc.target')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vect_str_zero.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_str_zero.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_str_zero.c new file mode 100644 index 0000000..07198de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_str_zero.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +#include <arm_neon.h> + +void +f (uint32x4_t *p) +{ + uint32x4_t x = { 0, 0, 0, 0}; + p[1] = x; + + /* { dg-final { scan-assembler "stp\txzr, xzr," } } */ +} + +void +g (float32x2_t *p) +{ + float32x2_t x = {0.0, 0.0}; + p[0] = x; + + /* { dg-final { scan-assembler "str\txzr, " } } */ +} |