fold-vec-cntlz-int.c: New.

	2017-08-09  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-cntlz-int.c: New.
	* gcc.target/powerpc/fold-vec-cntlz-char.c: New.
	* gcc.target/powerpc/fold-vec-cntlz-short.c: New.
	* gcc.target/powerpc/fold-vec-cntlz-longlong.c: New.

From-SVN: r250995

4 files changed, 88 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c
new file mode 100644
index 0000000..61dfbcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_cntlz with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testsc_h (vector signed char vsc2)
+{
+  return vec_cntlz (vsc2);
+}
+
+vector unsigned char
+testuc_h (vector unsigned char vuc2)
+{
+  return vec_cntlz (vuc2);
+}
+
+/* { dg-final { scan-assembler-times "vclzb" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c
new file mode 100644
index 0000000..ae4dd57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_cntlz with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsi (vector signed int vsi2)
+{
+  return vec_cntlz (vsi2);
+}
+
+vector unsigned int
+testui (vector unsigned int vui2)
+{
+  return vec_cntlz (vui2);
+}
+
+/* { dg-final { scan-assembler-times "vclzw" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c
new file mode 100644
index 0000000..1a72a2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_cntlz with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mvsx -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl (vector signed long long vsl2)
+{
+  return vec_cntlz (vsl2);
+}
+
+vector unsigned long long
+testul (vector unsigned long long vul2)
+{
+  return vec_cntlz (vul2);
+}
+
+/* { dg-final { scan-assembler-times "vclzd" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c
new file mode 100644
index 0000000..0f05cac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_cntlz with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testsi (vector signed short vss2)
+{
+  return vec_cntlz (vss2);
+}
+
+vector unsigned short
+testui (vector unsigned short vus2)
+{
+  return vec_cntlz (vus2);
+}
+
+/* { dg-final { scan-assembler-times "vclzh" 2 } } */