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| author | Eric Botcazou <ebotcazou@adacore.com> | 2023-03-28 10:13:24 +0200 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@adacore.com> | 2023-03-28 10:42:44 +0200 |
| commit | 6f2bb57f909014618aaf770bfaaf49e28e410311 (patch) | |
| tree | 5552c3f2013c811dc99883a33250d0618eadef9c /gcc/testsuite/gcc.target | |
| parent | 19b4d4801cd8d30cff4c1c26f816882cd56619aa (diff) | |
| download | gcc-6f2bb57f909014618aaf770bfaaf49e28e410311.zip gcc-6f2bb57f909014618aaf770bfaaf49e28e410311.tar.gz gcc-6f2bb57f909014618aaf770bfaaf49e28e410311.tar.bz2 | |
Fix PR target/109140
This is a regression present on the mainline and 12 branch at -O2, but the
issue is related to vectorization so was present at -O3 in earlier versions.
The vcondu expander that was added for VIS 3 more than a decade ago does not
fully work, because it does not filter out the unsigned condition codes (the
instruction is an UNSPEC that accepts only signed condition codes).
While I was at it, I also added the missing vcond and vcondu expanders for
the new comparison instructions that were added in VIS 4.
gcc/
PR target/109140
* config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition
on operand #3 to get the final condition code. Use std::swap.
* config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander.
(fucmp<gcond:code>8<P:mode>_vis): Move around.
(fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Likewise.
(vcondu<GCM:mode><GCM:mode>): New VIS 4 expander.
gcc/testsuite/
* gcc.target/sparc/20230328-1.c: New test.
* gcc.target/sparc/20230328-2.c: Likewise.
* gcc.target/sparc/20230328-3.c: Likewise.
* gcc.target/sparc/20230328-4.c: Likewise.
Diffstat (limited to 'gcc/testsuite/gcc.target')
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/20230328-1.c | 19 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/20230328-2.c | 19 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/20230328-3.c | 19 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/20230328-4.c | 19 |
4 files changed, 76 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-1.c b/gcc/testsuite/gcc.target/sparc/20230328-1.c new file mode 100644 index 0000000..bc0e35f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-1.c @@ -0,0 +1,19 @@ +/* PR target/109140 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mvis3 -std=c99" } */
+
+#define TYPE unsigned char
+
+struct S { TYPE ub[8]; };
+
+struct S s;
+
+TYPE v;
+
+void foo (void)
+{
+ for (int i = 0; i < 8; i++)
+ s.ub[i] = s.ub[i] > v;
+}
+
+/* { dg-final { scan-assembler "fucmpgt8\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-2.c b/gcc/testsuite/gcc.target/sparc/20230328-2.c new file mode 100644 index 0000000..7030344 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-2.c @@ -0,0 +1,19 @@ +/* PR target/109140 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mvis4 -std=c99" } */
+
+#define TYPE char
+
+struct S { TYPE ub[8]; };
+
+struct S s;
+
+TYPE v;
+
+void foo (void)
+{
+ for (int i = 0; i < 8; i++)
+ s.ub[i] = s.ub[i] > v;
+}
+
+/* { dg-final { scan-assembler "fpcmpgt8\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-3.c b/gcc/testsuite/gcc.target/sparc/20230328-3.c new file mode 100644 index 0000000..23d281e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-3.c @@ -0,0 +1,19 @@ +/* PR target/109140 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mvis4 -std=c99" } */
+
+#define TYPE unsigned short
+
+struct S { TYPE ub[4]; };
+
+struct S s;
+
+TYPE v;
+
+void foo (void)
+{
+ for (int i = 0; i < 4; i++)
+ s.ub[i] = s.ub[i] > v;
+}
+
+/* { dg-final { scan-assembler "fpcmpugt16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-4.c b/gcc/testsuite/gcc.target/sparc/20230328-4.c new file mode 100644 index 0000000..0172d0b --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-4.c @@ -0,0 +1,19 @@ +/* PR target/109140 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mvis3 -std=c99" } */
+
+#define TYPE short
+
+struct S { TYPE ub[4]; };
+
+struct S s;
+
+TYPE v;
+
+void foo (void)
+{
+ for (int i = 0; i < 4; i++)
+ s.ub[i] = s.ub[i] > v;
+}
+
+/* { dg-final { scan-assembler "fcmpgt16\t%" } } */
|