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| author | Alex Coplan <alex.coplan@arm.com> | 2023-02-06 14:32:21 +0000 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2023-02-20 09:18:41 +0000 |
| commit | 5b99b0f1ee65ad50b5e6d3a57aace616273cc814 (patch) | |
| tree | 98d7f165bb7ac178f87bc00bc19564918ff41d79 /gcc/testsuite/gcc.target | |
| parent | c6e3ecca0e3dcf567d0c843a4987e52591041372 (diff) | |
| download | gcc-5b99b0f1ee65ad50b5e6d3a57aace616273cc814.zip gcc-5b99b0f1ee65ad50b5e6d3a57aace616273cc814.tar.gz gcc-5b99b0f1ee65ad50b5e6d3a57aace616273cc814.tar.bz2 | |
aarch64: Fix up bfmlal lane pattern [PR104921]
As the testcase shows, this pattern had an incorrect constraint leading
to GCC's output getting rejected by the assembler.
This patch fixes the constraint accordingly.
The test is split into two: one that can run without bf16 support from
the assembler and another that checks that the output actually assembles
when such support is available.
gcc/ChangeLog:
PR target/104921
* config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
Use correct constraint for operand 3.
gcc/testsuite/ChangeLog:
PR target/104921
* gcc.target/aarch64/pr104921-1.c: New test.
* gcc.target/aarch64/pr104921-2.c: New test.
* gcc.target/aarch64/pr104921.x: Include file for new tests.
(cherry picked from commit 277e1f30a5e4e634304a7b8a532825119f0ea47f)
Diffstat (limited to 'gcc/testsuite/gcc.target')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr104921-1.c | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr104921-2.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr104921.x | 9 |
3 files changed, 27 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-1.c b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c new file mode 100644 index 0000000..dcf6fe7d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -march=armv8.2-a+bf16 -std=gnu99 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "pr104921.x" + +/* +**foo: +** mov v([0-9]|1[0-5])\.8b, v16\.8b +** bfmlalb v0\.4s, v1\.8h, v([0-9]|1[0-5])\.h\[0\] +** ret +*/ diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-2.c b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c new file mode 100644 index 0000000..211fcd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c @@ -0,0 +1,6 @@ +/* { dg-do assemble } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-O2 -std=gnu99" } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ + +#include "pr104921.x" diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921.x b/gcc/testsuite/gcc.target/aarch64/pr104921.x new file mode 100644 index 0000000..1e1a6f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr104921.x @@ -0,0 +1,9 @@ +#include <arm_neon.h> + +float32x4_t +foo(float32x4_t x, bfloat16x8_t a) +{ + register bfloat16x4_t b asm ("v16"); + asm volatile ("" : "=w"(b)); + return vbfmlalbq_lane_f32 (x, a, b, 0); +} |