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authorRichard Sandiford <richard.sandiford@arm.com>2023-04-03 09:57:06 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2023-04-03 09:57:06 +0100
commit33a69d0b0b772610463d1d586f3f0c9820fc969e (patch)
treed49243bcd70e13af80b6b57c98e0253a2623c869 /gcc/testsuite/gcc.target
parent160c5f354a6dc8a660ff8ad8574279b0d3fb412d (diff)
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vect: Fix voluntarily-masked negative conditionals [PR108430]
vectorizable_condition checks whether a COND_EXPR condition is used elsewhere with a loop mask. If so, it applies the loop mask to the COND_EXPR too, to reduce the number of live masks and to increase the chance of combining the AND with the comparison. There is also code to do this for inverted conditions. E.g. if we have a < b ? c : d and something else is conditional on !(a < b) (such as a load in d), we use !(a < b) ? d : c and apply the loop mask to !(a < b). This inversion relied on the function's bitop1/bitop2 mechanism. However, that mechanism is skipped if the condition is split out of the COND_EXPR as a separate statement. This meant that we could end up using the inverse of the intended condition. There is a separate way of negating the condition when a mask is being applied (which is also used for EXTRACT_LAST reductions). This patch uses that instead. As well as the testcase, this fixes aarch64/sve/vcond_{4,17}_run.c. gcc/ PR tree-optimization/108430 * tree-vect-stmts.cc (vectorizable_condition): Fix handling of inverted condition. gcc/testsuite/ PR tree-optimization/108430 * gcc.target/aarch64/sve/pr108430.c: New test. (cherry picked from commit 2a8ce4b52f5892a10a02b94d7be689e59a444ff6)
Diffstat (limited to 'gcc/testsuite/gcc.target')
-rw-r--r--gcc/testsuite/gcc.target/aarch64/sve/pr108430.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr108430.c b/gcc/testsuite/gcc.target/aarch64/sve/pr108430.c
new file mode 100644
index 0000000..e7ce0f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr108430.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target aarch64_sve512_hw } } */
+/* { dg-options "-O3 -msve-vector-bits=512" } */
+
+long d = 1;
+static int i = 37;
+static unsigned long a[22];
+static unsigned short c[22];
+static unsigned g[80];
+static unsigned short *h = c;
+static unsigned long *j = a;
+int main() {
+ for (long m = 0; m < 8; ++m)
+ d = 1;
+ for (unsigned char p = 0; p < 17; p += 2)
+ {
+ long t = h[p] ? i : j[p];
+ g[p] = t;
+ }
+ if (g[0])
+ __builtin_abort ();
+}