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authorRobin Dapp <rdapp@ventanamicro.com>2024-03-06 12:15:40 +0100
committerRobin Dapp <rdapp@ventanamicro.com>2024-03-06 20:30:15 +0100
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RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].
Three-operand instructions like vmacc are modeled with an implicit output reload when the output does not match one of the operands. For this we use vmv.v.v which is subject to length masking. In a situation where the current vl is less than the full vlenb and the fma's result value is used as input for a vector reduction (which is never length masked) we effectively only reduce vl elements. The masked-out elements are relevant for the reduction, though, leading to a wrong result. This patch replaces the vmv reloads by full-register reloads. gcc/ChangeLog: PR target/114200 PR target/114202 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114200.c: New test. * gcc.target/riscv/rvv/autovec/pr114202.c: New test.
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