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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-11-10 00:43:05 +0100
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-11-10 14:57:02 +0100
commit2f6cb9c51a933de19cd88f4c9180ac9cf5093522 (patch)
treefa7d78125227177882b17534e6e31dfcd3f2c555 /gcc/system.h
parent203b127fccc9abe5373c9e3cc03a476c35b1f594 (diff)
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RISC-V: Fix selection of pipeline model for sifive-7-series
A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a while now, due to the pipeline model for sifive-7-series not being selected despite -mtune=sifive-7-series. The root cause is that the respective RISCV_TUNE entry points to generic instead. Fix this. Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune") gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Update sifive-7-series to point to the sifive_7 pipeline description.
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