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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-12-27 23:19:15 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-12-27 23:19:15 +0000 |
| commit | df3aba14abea0890c5429b8c7631e827e0e61cef (patch) | |
| tree | 126000d460d63ca5b7f997a560a4cbd5d8295e2a /gcc/sreal.c | |
| parent | 41a38208bc0acadf94bd5c6684065d6dc61d951a (diff) | |
| download | gcc-df3aba14abea0890c5429b8c7631e827e0e61cef.zip gcc-df3aba14abea0890c5429b8c7631e827e0e61cef.tar.gz gcc-df3aba14abea0890c5429b8c7631e827e0e61cef.tar.bz2 | |
predicates.md (const_0_to_12_operand): Rename predicate and change test from 0..11 to 0..12 to match the semantics of...
[gcc]
2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (const_0_to_12_operand): Rename
predicate and change test from 0..11 to 0..12 to match the
semantics of the word extract/insert instructions. Change all
callers.
(const_0_to_11_operand): Likewise.
* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
* config/rs6000/vsx.md (vextract4b): Likewise.
(vextract4b_internal): Likewise.
(vinsert4b): Likewise.
(vinsert4b_internal): Likewise.
(vinsert4b_di): Likewise.
(vinsert4b_di_internal): Likewise.
* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
in xxextractuw to zero extend the word in the vector registers.
(lfiwzx): Likewise.
[gcc/testsuite]
2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
being out of bounds instead of 12.
From-SVN: r243948
Diffstat (limited to 'gcc/sreal.c')
0 files changed, 0 insertions, 0 deletions