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| author | Alex Velenko <Alex.Velenko@arm.com> | 2014-11-05 11:22:28 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2014-11-05 11:22:28 +0000 |
| commit | 96023bbaff939ca5fe957688a940f045201c55c1 (patch) | |
| tree | 22ea68efbe565c6d94846fa9b5ecbb5f410b0749 /gcc/simplify-rtx.c | |
| parent | 8c7686294ebecda8d3801e0a38ba174c9b527f8f (diff) | |
| download | gcc-96023bbaff939ca5fe957688a940f045201c55c1.zip gcc-96023bbaff939ca5fe957688a940f045201c55c1.tar.gz gcc-96023bbaff939ca5fe957688a940f045201c55c1.tar.bz2 | |
simplify-rtx.c (simplify_binary_operation_1): Div check added.
2014-11-05 Alex Velenko <Alex.Velenko@arm.com>
gcc/
* simplify-rtx.c (simplify_binary_operation_1): Div check added.
* rtl.h (SUBREG_P): New macro added.
gcc/testsuite/
* gcc.dg/asr-div1.c: New testcase.
From-SVN: r217118
Diffstat (limited to 'gcc/simplify-rtx.c')
| -rw-r--r-- | gcc/simplify-rtx.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index 1e4ba23..8094c75 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -3104,6 +3104,44 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, && UINTVAL (trueop0) == GET_MODE_MASK (mode) && ! side_effects_p (op1)) return op0; + /* Given: + scalar modes M1, M2 + scalar constants c1, c2 + size (M2) > size (M1) + c1 == size (M2) - size (M1) + optimize: + (ashiftrt:M1 (subreg:M1 (lshiftrt:M2 (reg:M2) + (const_int <c1>)) + <low_part>) + (const_int <c2>)) + to: + (subreg:M1 (ashiftrt:M2 (reg:M2) + (const_int <c1 + c2>)) + <low_part>). */ + if (!VECTOR_MODE_P (mode) + && SUBREG_P (op0) + && CONST_INT_P (op1) + && (GET_CODE (SUBREG_REG (op0)) == LSHIFTRT) + && !VECTOR_MODE_P (GET_MODE (SUBREG_REG (op0))) + && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)) + && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) + > GET_MODE_BITSIZE (mode)) + && (INTVAL (XEXP (SUBREG_REG (op0), 1)) + == (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) + - GET_MODE_BITSIZE (mode))) + && subreg_lowpart_p (op0)) + { + rtx tmp = GEN_INT (INTVAL (XEXP (SUBREG_REG (op0), 1)) + + INTVAL (op1)); + machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); + tmp = simplify_gen_binary (ASHIFTRT, + GET_MODE (SUBREG_REG (op0)), + XEXP (SUBREG_REG (op0), 0), + tmp); + return simplify_gen_subreg (mode, tmp, inner_mode, + subreg_lowpart_offset (mode, + inner_mode)); + } canonicalize_shift: if (SHIFT_COUNT_TRUNCATED && CONST_INT_P (op1)) { |