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authorH.J. Lu <hongjiu.lu@intel.com>2018-10-18 08:18:42 +0000
committerH.J. Lu <hjl@gcc.gnu.org>2018-10-18 01:18:42 -0700
commit294973a49751a7fc2d6a7a9f2749ce851a368c04 (patch)
tree3a5176da419a68ba632eb29ab9f43065afcc053e /gcc/simplify-rtx.c
parent7702ab653a903d5131bf72244ae22424ffd2e6c7 (diff)
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Simplify subreg of vec_merge of vec_duplicate
We can simplify (subreg (vec_merge (vec_duplicate X) (vector) (const_int ((1 << N) | M))) (N * sizeof (X))) to X when mode of X is the same as of mode of subreg. gcc/ PR target/87537 * simplify-rtx.c (simplify_subreg): Simplify subreg of vec_merge of vec_duplicate. (test_vector_ops_duplicate): Add test for a scalar subreg of a VEC_MERGE of a VEC_DUPLICATE. gcc/testsuite/ PR target/87537 * gcc.target/i386/pr87537-1.c: New test. From-SVN: r265260
Diffstat (limited to 'gcc/simplify-rtx.c')
-rw-r--r--gcc/simplify-rtx.c29
1 files changed, 28 insertions, 1 deletions
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 9bc5386..b0cf3bb 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -6601,6 +6601,21 @@ simplify_subreg (machine_mode outermode, rtx op,
return NULL_RTX;
}
+ /* Return X for
+ (subreg (vec_merge (vec_duplicate X)
+ (vector)
+ (const_int ((1 << N) | M)))
+ (N * sizeof (X)))
+ */
+ unsigned int idx;
+ if (constant_multiple_p (byte, GET_MODE_SIZE (outermode), &idx)
+ && GET_CODE (op) == VEC_MERGE
+ && GET_CODE (XEXP (op, 0)) == VEC_DUPLICATE
+ && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode
+ && CONST_INT_P (XEXP (op, 2))
+ && (UINTVAL (XEXP (op, 2)) & (HOST_WIDE_INT_1U << idx)) != 0)
+ return XEXP (XEXP (op, 0), 0);
+
/* A SUBREG resulting from a zero extension may fold to zero if
it extracts higher bits that the ZERO_EXTEND's source bits. */
if (GET_CODE (op) == ZERO_EXTEND && SCALAR_INT_MODE_P (innermode))
@@ -6831,15 +6846,27 @@ test_vector_ops_duplicate (machine_mode mode, rtx scalar_reg)
simplify_binary_operation (VEC_SELECT, inner_mode,
duplicate, zero_par));
- /* And again with the final element. */
unsigned HOST_WIDE_INT const_nunits;
if (nunits.is_constant (&const_nunits))
{
+ /* And again with the final element. */
rtx last_index = gen_int_mode (const_nunits - 1, word_mode);
rtx last_par = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, last_index));
ASSERT_RTX_PTR_EQ (scalar_reg,
simplify_binary_operation (VEC_SELECT, inner_mode,
duplicate, last_par));
+
+ /* Test a scalar subreg of a VEC_MERGE of a VEC_DUPLICATE. */
+ rtx vector_reg = make_test_reg (mode);
+ for (unsigned HOST_WIDE_INT i = 0; i < const_nunits; i++)
+ {
+ rtx mask = GEN_INT ((HOST_WIDE_INT_1U << i) | (i + 1));
+ rtx vm = gen_rtx_VEC_MERGE (mode, duplicate, vector_reg, mask);
+ poly_uint64 offset = i * GET_MODE_SIZE (inner_mode);
+ ASSERT_RTX_EQ (scalar_reg,
+ simplify_gen_subreg (inner_mode, vm,
+ mode, offset));
+ }
}
/* Test a scalar subreg of a VEC_DUPLICATE. */