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| author | Jeff Law <jeffreyalaw@gmail.com> | 2022-10-16 12:43:25 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2022-10-16 12:43:25 -0400 |
| commit | 6366e3e8847af98d4728d55951534769d034d02a (patch) | |
| tree | 3f95e3a96125948f2535b5e6cd22c85d01dec018 /gcc/sched-vis.c | |
| parent | 709b2160bcd8f6f57c8754c73d40550895339c7b (diff) | |
| download | gcc-6366e3e8847af98d4728d55951534769d034d02a.zip gcc-6366e3e8847af98d4728d55951534769d034d02a.tar.gz gcc-6366e3e8847af98d4728d55951534769d034d02a.tar.bz2 | |
Add new constraints for upcoming autoinc fixes
GCC does not allow a the operand of an autoinc addressing mode to
overlap with another soure operand in the same insn. This is primarly
enforced with insn conditions. However, cases can slip through LRA
and reload. To address those scenarios we'll take an idea from the
pdp11 port for describing the restriction in constraints as well.
To implement that we need register classes and constraints which are
"all general purpose hardware registers except r0". And similarly for
r1..r7(sp).
This patch adds those register classes and constraints, but does not
yet use them.
gcc/
* config/h8300/constraints.md (Z0..Z7): New register
constraints.
* config/h8300/h8300.h (reg_class): Add new classes.
(REG_CLASS_NAMES): Similarly.
(REG_CLASS_CONTENTS): Similarly.
Diffstat (limited to 'gcc/sched-vis.c')
0 files changed, 0 insertions, 0 deletions