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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-12-14 16:15:48 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-12-19 22:23:22 +0800 |
| commit | 76023293e6e82439643048a32cad36ddf9ba0e44 (patch) | |
| tree | ae0c28f55a51ce45ce7bdad7510fd9d9fcb688ef /gcc/rust/resolve | |
| parent | 6f18836ca035d3d029cdc503e2a0d7d685a4d072 (diff) | |
| download | gcc-76023293e6e82439643048a32cad36ddf9ba0e44.zip gcc-76023293e6e82439643048a32cad36ddf9ba0e44.tar.gz gcc-76023293e6e82439643048a32cad36ddf9ba0e44.tar.bz2 | |
RISC-V: Add testcases for VSETVL PASS 3
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: New test.
Diffstat (limited to 'gcc/rust/resolve')
0 files changed, 0 insertions, 0 deletions