diff options
| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-12-14 15:01:56 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-12-19 22:09:35 +0800 |
| commit | 22dc669e109de9a76c74535cdf30e7922e0ef5c1 (patch) | |
| tree | e5929ec0e5d29465f14c020df1d9e44b30f5643f /gcc/rust/resolve | |
| parent | 6e85f89a7d59a99a3395b6e153b99262a58b2f6c (diff) | |
| download | gcc-22dc669e109de9a76c74535cdf30e7922e0ef5c1.zip gcc-22dc669e109de9a76c74535cdf30e7922e0ef5c1.tar.gz gcc-22dc669e109de9a76c74535cdf30e7922e0ef5c1.tar.bz2 | |
RISC-V: Fix RVV machine mode attribute configuration
The attribute configuration of each machine mode are support in the previous patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
Diffstat (limited to 'gcc/rust/resolve')
0 files changed, 0 insertions, 0 deletions