RISC-V: vsetvl: Refine REG_EQUAL equality.

This patch enhances the equality check for REG_EQUAL notes in the vsetvl
pass by using the == operator instead of rtx_equal_p.  With that, in
situations like the following, a5 and a7 are not considered equal
anymore.

(insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154])
        (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (const_int 8 [0x8]))
        (nil)))
(insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175])
        (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3}
     (nil))
(insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153])
        (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (const_int 8 [0x8]))
        (nil)))

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
	equality for REG_EQUAL.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: New test.

0 files changed, 0 insertions, 0 deletions