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| author | Xi Ruoyao <xry111@xry111.site> | 2023-11-16 09:30:14 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2023-11-19 01:11:13 +0800 |
| commit | 181ed726b22afc3e2897447d0631ef0bcc2d106d (patch) | |
| tree | 840fe90d262c120efb82275c374c3de2488686d1 /gcc/rust/resolve | |
| parent | 5d3d60555346edd93a544d4f80a1eb1f8117808c (diff) | |
| download | gcc-181ed726b22afc3e2897447d0631ef0bcc2d106d.zip gcc-181ed726b22afc3e2897447d0631ef0bcc2d106d.tar.gz gcc-181ed726b22afc3e2897447d0631ef0bcc2d106d.tar.bz2 | |
LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other". Thus
we can omit the "load-load" barrier dbar 0x700.
This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
print dbar 0x700 if TARGET_LD_SEQ_SA.
* config/loongarch/sync.md (atomic_load<mode>): Likewise.
Diffstat (limited to 'gcc/rust/resolve')
0 files changed, 0 insertions, 0 deletions