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| author | Robin Dapp <rdapp@ventanamicro.com> | 2023-12-05 15:24:12 +0100 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2023-12-06 10:27:48 +0100 |
| commit | 056cce412862f8d9b56a40dfbcbc3f9fa7f92883 (patch) | |
| tree | bdfd043a2b6bb56bbaf5cec085d42b7c7f584a2c /gcc/rust/resolve | |
| parent | e44ed92dbbe9d4e5c23f486cd2f77a6f9ee513c5 (diff) | |
| download | gcc-056cce412862f8d9b56a40dfbcbc3f9fa7f92883.zip gcc-056cce412862f8d9b56a40dfbcbc3f9fa7f92883.tar.gz gcc-056cce412862f8d9b56a40dfbcbc3f9fa7f92883.tar.bz2 | |
RISC-V: Add vec_init expander for masks [PR112854].
PR112854 shows a problem on rv32 with zvl1024b. During the course of
expand_constructor we try to overlay/subreg a 64-element mask by a
scalar (Pmode) register. This works for zvl512b and its maximum of
32 elements but fails for rv32 and 64 elements.
To circumvent this this patch adds a vec_init expander for vector masks
by initializing a QImode vector and comparing that against 0.
gcc/ChangeLog:
PR target/112854
PR target/112872
* config/riscv/autovec.md (vec_init<mode>qi): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112854.c: New test.
* gcc.target/riscv/rvv/autovec/pr112872.c: New test.
Diffstat (limited to 'gcc/rust/resolve')
0 files changed, 0 insertions, 0 deletions