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| author | Xi Ruoyao <xry111@xry111.site> | 2023-11-16 09:21:47 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2023-11-19 01:11:12 +0800 |
| commit | 5d3d60555346edd93a544d4f80a1eb1f8117808c (patch) | |
| tree | 5c9bcb6f1192f44b83914b446326575501dbf385 /gcc/rust/resolve/rust-ast-resolve-expr.cc | |
| parent | ccead01d9bd253cb21b61884d4d20f42a2feee31 (diff) | |
| download | gcc-5d3d60555346edd93a544d4f80a1eb1f8117808c.zip gcc-5d3d60555346edd93a544d4f80a1eb1f8117808c.tar.gz gcc-5d3d60555346edd93a544d4f80a1eb1f8117808c.tar.bz2 | |
LoongArch: Take the advantage of -mdiv32 if it's enabled
With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
of a 64-bit GPR even if it's not sign-extended.
gcc/ChangeLog:
* config/loongarch/loongarch.md (DIV): New mode iterator.
(<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
(<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
(*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
(<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/div-div32.c: New test.
* gcc.target/loongarch/div-no-div32.c: New test.
Diffstat (limited to 'gcc/rust/resolve/rust-ast-resolve-expr.cc')
0 files changed, 0 insertions, 0 deletions