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| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-09-15 19:39:43 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-23 23:37:17 +0800 |
| commit | b2fe02b476afc1cddb3abcf26ec4b1e072a9401b (patch) | |
| tree | e1d9c8a0c4b3b916f22a3b6c842291dca16effc4 /gcc/rust/backend | |
| parent | b4feb49cf308b344fba6a72137df58de382fcb9d (diff) | |
| download | gcc-b2fe02b476afc1cddb3abcf26ec4b1e072a9401b.zip gcc-b2fe02b476afc1cddb3abcf26ec4b1e072a9401b.tar.gz gcc-b2fe02b476afc1cddb3abcf26ec4b1e072a9401b.tar.bz2 | |
RISC-V: Add RVV machine modes.
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes.
(ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks.
(ADJUST_ALIGNMENT): Adjust alignment.
(ADJUST_BYTESIZE): Adjust bytesize using riscv_vector_chunks.
(RVV_MODES): New macro.
(VECTOR_MODE_WITH_PREFIX): Add RVV vector modes.
(VECTOR_MODES_WITH_PREFIX): Add RVV vector modes.
Diffstat (limited to 'gcc/rust/backend')
0 files changed, 0 insertions, 0 deletions