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| author | Eric Botcazou <ebotcazou@adacore.com> | 2018-09-19 10:12:04 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2018-09-19 10:12:04 +0000 |
| commit | 574f5885f7d0fce6cb7f3b0bcf476871722d0bc9 (patch) | |
| tree | ce5be239ac6c64a46b6ea8337b16f0b6248e2b93 /gcc/rtlanal.c | |
| parent | d4eb08fe028d95d6e4055c96f7fa40517653c30c (diff) | |
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re PR rtl-optimization/87361 (gcc.target/sparc/20161111-1.c FAILs)
PR rtl-optimization/87361
* rtlanal.c (nonzero_bits1): Revert accidental change.
From-SVN: r264420
Diffstat (limited to 'gcc/rtlanal.c')
| -rw-r--r-- | gcc/rtlanal.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 366df7c..e8b6b9c 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4758,17 +4758,17 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); - /* On many CISC machines, accessing an object in a wider mode + /* On many CISC machines, accessing an object in a wider mode causes the high-order bits to become undefined. So they are not known to be zero. */ rtx_code extend_op; if ((!WORD_REGISTER_OPERATIONS /* If this is a typical RISC machine, we only have to worry about the way loads are extended. */ - || !MEM_P (SUBREG_REG (x)) || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) - : extend_op != ZERO_EXTEND)) + : extend_op != ZERO_EXTEND) + || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x)))) && xmode_width > inner_width) nonzero |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode)); |