always define WORD_REGISTER_OPERATIONS

gcc/ChangeLog:

2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
	* config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
	* config/arc/arc.h: Likewise.
	* config/arm/arm.h: Likewise.
	* config/bfin/bfin.h: Likewise.
	* config/epiphany/epiphany.h: Likewise.
	* config/frv/frv.h: Likewise.
	* config/ia64/ia64.h: Likewise.
	* config/iq2000/iq2000.h: Likewise.
	* config/lm32/lm32.h: Likewise.
	* config/m32r/m32r.h: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/mep/mep.h: Likewise.
	* config/microblaze/microblaze.h: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mmix/mmix.h: Likewise.
	* config/mn10300/mn10300.h: Likewise.
	* config/nds32/nds32.h: Likewise.
	* config/nios2/nios2.h: Likewise.
	* config/pa/pa.h: Likewise.
	* config/rl78/rl78.h: Likewise.
	* config/sh/sh.h: Likewise.
	* config/sparc/sparc.h: Likewise.
	* config/stormy16/stormy16.h: Likewise.
	* config/tilegx/tilegx.h: Likewise.
	* config/tilepro/tilepro.h: Likewise.
	* config/v850/v850.h: Likewise.
	* config/xtensa/xtensa.h: Likewise.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in: Adjust.
	* combine.c (simplify_set): Likewise.
	(simplify_comparison): Likewise.
	* expr.c (store_constructor): Likewise.
	* internal-fn.c (expand_arith_overflow): Likewise.
	* reload.c (push_reload): Likewise.
	(find_reloads): Likewise.
	(find_reloads_subreg_address): Likewise.
	* reload1.c (eliminate_regs_1): Likewise.
	* rtlanal.c (nonzero_bits1): Likewise.
	(num_sign_bit_copies1): Likewise.
	* simplify-rtx.c (simplify_truncation): Likewise.

From-SVN: r225597

1 files changed, 9 insertions, 11 deletions

diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index e910ae7..cb20c25 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4253,7 +4253,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
        just return the mode mask.  Those tests will then be false.  */
     return nonzero;
 
-#ifndef WORD_REGISTER_OPERATIONS
   /* If MODE is wider than X, but both are a single word for both the host
      and target machines, we can compute this from which bits of the
      object might be nonzero in its own mode, taking into account the fact
@@ -4261,7 +4260,9 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
      causes the high-order bits to become undefined.  So they are
      not known to be zero.  */
 
-  if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
+  if (!WORD_REGISTER_OPERATIONS
+      && GET_MODE (x) != VOIDmode
+      && GET_MODE (x) != mode
       && GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD
       && GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
       && GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x)))
@@ -4271,7 +4272,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
       nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
       return nonzero;
     }
-#endif
 
   code = GET_CODE (x);
   switch (code)
@@ -4543,7 +4543,7 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
 	  nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
 					  known_x, known_mode, known_ret);
 
-#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
+#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
 	  /* If this is a typical RISC machine, we only have to worry
 	     about the way loads are extended.  */
 	  if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
@@ -4763,12 +4763,12 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 
   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x)))
     {
-#ifndef WORD_REGISTER_OPERATIONS
       /* If this machine does not do all register operations on the entire
 	 register and MODE is wider than the mode of X, we can say nothing
 	 at all about the high-order bits.  */
-      return 1;
-#else
+      if (!WORD_REGISTER_OPERATIONS)
+	return 1;
+
       /* Likewise on machines that do, if the mode of the object is smaller
 	 than a word and loads of that size don't sign extend, we can say
 	 nothing about the high order bits.  */
@@ -4778,7 +4778,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 #endif
 	  )
 	return 1;
-#endif
     }
 
   switch (code)
@@ -4857,7 +4856,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 				   - bitwidth)));
 	}
 
-#ifdef WORD_REGISTER_OPERATIONS
 #ifdef LOAD_EXTEND_OP
       /* For paradoxical SUBREGs on machines where all register operations
 	 affect the entire register, just look inside.  Note that we are
@@ -4869,13 +4867,13 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 	 then we lose all sign bit copies that existed before the store
 	 to the stack.  */
 
-      if (paradoxical_subreg_p (x)
+      if (WORD_REGISTER_OPERATIONS
+	  && paradoxical_subreg_p (x)
 	  && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
 	  && MEM_P (SUBREG_REG (x)))
 	return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
 					   known_x, known_mode, known_ret);
 #endif
-#endif
       break;
 
     case SIGN_EXTRACT: