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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-06-02 10:04:47 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-02 15:27:46 +0800 |
| commit | a06b9435b9652ea1b0d30e6fa176c91df314954f (patch) | |
| tree | 281dc9973498e36194a0b1f9f4b98bb472637601 /gcc/rtl.h | |
| parent | 265357d401fb7215e8fea820d29a48eacdd75ad1 (diff) | |
| download | gcc-a06b9435b9652ea1b0d30e6fa176c91df314954f.zip gcc-a06b9435b9652ea1b0d30e6fa176c91df314954f.tar.gz gcc-a06b9435b9652ea1b0d30e6fa176c91df314954f.tar.bz2 | |
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
Base on these:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233
Add _mu C++ overloaded intrinsics for load && viota && vid.
Co-authored-by: KuanLin Chen <best124612@gmail.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Add _mu overloaded intrinsics.
* config/riscv/riscv-vector-builtins-shapes.cc (struct fault_load_def): Ditto.
Diffstat (limited to 'gcc/rtl.h')
0 files changed, 0 insertions, 0 deletions