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| author | Jim Wilson <jimw@sifive.com> | 2018-04-02 22:37:21 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-04-02 15:37:21 -0700 |
| commit | b7ef9225f7f997a37f96a3a9c2eb31533865822b (patch) | |
| tree | 2b4c1d1ef35215676c1927b0b1a197e2a919dce6 /gcc/rtl.h | |
| parent | 82a926bf06e8b7989ee189ef2b3bf7a6c055d6b8 (diff) | |
| download | gcc-b7ef9225f7f997a37f96a3a9c2eb31533865822b.zip gcc-b7ef9225f7f997a37f96a3a9c2eb31533865822b.tar.gz gcc-b7ef9225f7f997a37f96a3a9c2eb31533865822b.tar.bz2 | |
RISC-V: Fix for combine bug with shift and AND operations.
PR rtl-optimization/84660
gcc/
* config/riscv/riscv.h (SHIFT_COUNT_TRUNCATED): Set to zero.
* config/riscv/riscv.md (<optab>si3): Use QImode shift count.
(<optab>di3, <optab>si3_extend): Likewise.
(<optab>si3_mask, <optab>si3_mask_1): New.
(<optab>di3_mask, <optab>di3_mask_1): New.
(<optab>si3_extend_mask, <optab>si3_extend_mask_1): New.
(lshrsi3_zero_extend_1): Use VOIDmode shift count.
* config/riscv/sync.md (atomic_test_and_set): Emit QImode shift count.
gcc/testsuite/
* gcc.target/riscv/pr84660.c: New.
* gcc.target/riscv/shift-and-1.c: New.
* gcc.target/riscv/shift-and-2.c: New.
From-SVN: r259019
Diffstat (limited to 'gcc/rtl.h')
0 files changed, 0 insertions, 0 deletions