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authorJeff Law <jlaw@ventanamicro.com>2024-06-20 08:43:37 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-06-20 08:43:37 -0600
commitf739ad5e35b0a60dec65bb12f8d07aadd0c98196 (patch)
treebcb3efe2535517b6fd6948b2ec9865818f67851c /gcc/rtl-tests.cc
parent1340ddea0158de3f49aeb75b4013e5fc313ff6f4 (diff)
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[RISC-V] Minor cleanup/improvement to bset/binv patterns
Changes since V1: Whitespace fixes noted by the linter Missed using the iterator for the output template in <bit_optab><mode>_mask pattern! -- This patch introduces a bit_optab iterator that maps IOR/XOR to bset and binv (and one day bclr if we need it). That allows us to combine some patterns that only differed in the RTL opcode (IOR vs XOR) and in the name/assembly (bset vs binv). Additionally this also allow us to use the iterator in the bset<mode>mask and bsetidisi patterns thus potentially fixing a missed optimization. This has gone through my tester. I'll wait for a verdict from pre-commit CI before moving forward. gcc/ * config/riscv/bitmanip.md (<bit_optab><mode>): New unified pattern for bset/binv using a code iterator. (<bit_optab>i<mode>): Likewise. (<bit_optab><mode>_mask): Likewise. Support XOR via any_or. (<bit_optab>isidi): Likewise. * config/riscv/iterators.md (bit_optab): New iterator.
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