diff options
| author | Alexander Monakov <amonakov@ispras.ru> | 2022-11-01 17:53:13 +0300 |
|---|---|---|
| committer | Alexander Monakov <amonakov@ispras.ru> | 2022-11-16 16:41:39 +0300 |
| commit | d4cc7a8c4a623b62dd0d486d7780d91b58eb6f1f (patch) | |
| tree | 98e6fc048db7a67a48e9ebcebb01a4abf2cb5169 /gcc/range-op-float.cc | |
| parent | dd744f06c9952f92738b0860630085f0f0b99574 (diff) | |
| download | gcc-d4cc7a8c4a623b62dd0d486d7780d91b58eb6f1f.zip gcc-d4cc7a8c4a623b62dd0d486d7780d91b58eb6f1f.tar.gz gcc-d4cc7a8c4a623b62dd0d486d7780d91b58eb6f1f.tar.bz2 | |
i386: correct x87&SSE multiplication modeling in znver.md
All multiplication instructions are fully pipelined, except AVX256
instructions on Zen 1, which issue over two cycles on a 128-bit unit.
Correct the model accordingly to reduce combinatorial explosion in
automaton tables.
Top znver table sizes in insn-automata.o:
Before:
30056 r znver1_fp_min_issue_delay
120224 r znver1_fp_transitions
After:
6720 r znver1_fp_min_issue_delay
53760 r znver1_fp_transitions
gcc/ChangeLog:
PR target/87832
* config/i386/znver.md: (znver1_fp_op_mul): Correct cycles in
the reservation.
(znver1_fp_op_mul_load): Ditto.
(znver1_mmx_mul): Ditto.
(znver1_mmx_load): Ditto.
(znver1_ssemul_ss_ps): Ditto.
(znver1_ssemul_ss_ps_load): Ditto.
(znver1_ssemul_avx256_ps): Ditto.
(znver1_ssemul_avx256_ps_load): Ditto.
(znver1_ssemul_sd_pd): Ditto.
(znver1_ssemul_sd_pd_load): Ditto.
(znver2_ssemul_sd_pd): Ditto.
(znver2_ssemul_sd_pd_load): Ditto.
(znver1_ssemul_avx256_pd): Ditto.
(znver1_ssemul_avx256_pd_load): Ditto.
(znver1_sseimul): Ditto.
(znver1_sseimul_avx256): Ditto.
(znver1_sseimul_load): Ditto.
(znver1_sseimul_avx256_load): Ditto.
(znver1_sseimul_di): Ditto.
(znver1_sseimul_load_di): Ditto.
Diffstat (limited to 'gcc/range-op-float.cc')
0 files changed, 0 insertions, 0 deletions