diff options
| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-20 16:07:49 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-20 18:36:15 +0800 |
| commit | c3d2b6bc913803d3eccacb9e354f37eef1cee212 (patch) | |
| tree | 9b56dfe51f8abc496de529231cd406aae083e264 /gcc/range-op-float.cc | |
| parent | 2e36eedb244badaaf2a70388071115c851b8db9b (diff) | |
| download | gcc-c3d2b6bc913803d3eccacb9e354f37eef1cee212.zip gcc-c3d2b6bc913803d3eccacb9e354f37eef1cee212.tar.gz gcc-c3d2b6bc913803d3eccacb9e354f37eef1cee212.tar.bz2 | |
RISC-V: Fix Demand comparison bug[VSETVL PASS]
This bug is exposed when we support VLS integer conversion patterns.
FAIL: c-c++-common/torture/pr53505.c execution.
This is because incorrect vsetvl elimination by Phase 4:
10318: 0d207057 vsetvli zero,zero,e32,m4,ta,ma
1031c: 5e003e57 vmv.v.i v28,0
.....: ........ missed e8,m1 vsetvl
10320: 7b07b057 vmsgtu.vi v0,v16,15
10324: 03083157 vadd.vi v2,v16,-16
Regression on release version GCC no surprise difference.
Committed.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Fix bug.
Diffstat (limited to 'gcc/range-op-float.cc')
0 files changed, 0 insertions, 0 deletions