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| author | Jia-Wei Chen <jiawei@iscas.ac.cn> | 2022-11-16 22:58:54 -0500 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2022-11-16 23:00:52 -0500 |
| commit | a62d957342e3e9ee9bda812f737279f1166e03ba (patch) | |
| tree | a59ee47de8a820f4386d88764b0e428a7947590d /gcc/range-op-float.cc | |
| parent | e214cab68cb34e77622b91113f7698cf137bbdd6 (diff) | |
| download | gcc-a62d957342e3e9ee9bda812f737279f1166e03ba.zip gcc-a62d957342e3e9ee9bda812f737279f1166e03ba.tar.gz gcc-a62d957342e3e9ee9bda812f737279f1166e03ba.tar.bz2 | |
RISC-V: Optimize RVV epilogue logic.
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
Do not emit useless add sp, sp, 0 instrutions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
Diffstat (limited to 'gcc/range-op-float.cc')
0 files changed, 0 insertions, 0 deletions