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| author | liuhongt <hongtao.liu@intel.com> | 2022-11-07 09:55:25 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-11-09 09:12:52 +0800 |
| commit | 916bec9a05ea522c81381e0c93590d46965d9c7b (patch) | |
| tree | abd62d69fe27dcf5226cfa27eedce2a068303d0a /gcc/range-op-float.cc | |
| parent | 69023a9f955dbb6dddca5d270379193a124bdf3c (diff) | |
| download | gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.zip gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.tar.gz gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.tar.bz2 | |
Fix incorrect insn type to avoid ICE in memory attr auto-detection.
Memory attribute auto detection will check operand 2 for type sselog,
and check operand 1 for type sselog1. For below 2 insns, there's no
operand 2. Change type to sselog1.
gcc/ChangeLog:
PR target/107540
* config/i386/sse.md (avx512f_movddup512<mask_name>): Change
type from sselog to sselog1.
(avx_movddup256<mask_name>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr107540.c: New test.
Diffstat (limited to 'gcc/range-op-float.cc')
0 files changed, 0 insertions, 0 deletions