RISC-V: Fix reload fail issue on vector mac instructions

Vector mac instructions has LRA issue during high register pressure,
It will failed to reload when picked first alternative, because it will
require reload 2 input operands into same register as input operand,
so we adding an extra operand to generate one more move pattern to
relax such restricted constraint.

This path fix ICE of ternary intrinsic:
bug.C:144:2: error: unable to find a register to spill
  144 |  }
      |  ^
bug.C:144:2: error: this is the insn:
(insn 462 972 919 24 (set (reg/v:VNx8DI 546 [orig:192 var_10 ] [192])
        (if_then_else:VNx8DI (unspec:VNx8BI [
                    (reg/v:VNx8BI 603 [orig:179 var_13 ] [179])
                    (const_int 13 [0xd])
                    (const_int 2 [0x2])
                    (const_int 0 [0]) repeated x2
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (plus:VNx8DI (mult:VNx8DI (reg/v:VNx8DI 605 [orig:190 var_6 ] [190])
                    (reg/v:VNx8DI 547 [orig:160 var_51 ] [160]))
                (reg/v:VNx8DI 548 [orig:161 var_52 ] [161]))
            (reg/v:VNx8DI 605 [orig:190 var_6 ] [190]))) "bug.C":131:48 4171 {*pred_maddvnx8di}
     (expr_list:REG_DEAD (reg/v:VNx8DI 605 [orig:190 var_6 ] [190])
        (expr_list:REG_DEAD (reg/v:VNx8BI 603 [orig:179 var_13 ] [179])
            (expr_list:REG_DEAD (reg/v:VNx8DI 547 [orig:160 var_51 ] [160])
                (expr_list:REG_DEAD (reg/v:VNx8DI 548 [orig:161 var_52 ] [161])
                    (nil))))))

gcc/ChangeLog:

	* config/riscv/vector.md: Fix RA constraint.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-19.C: New test.
	* g++.target/riscv/rvv/base/bug-20.C: New test.
	* g++.target/riscv/rvv/base/bug-21.C: New test.
	* g++.target/riscv/rvv/base/bug-22.C: New test.

Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>

0 files changed, 0 insertions, 0 deletions