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| author | Pan Li <pan2.li@intel.com> | 2023-06-12 15:16:21 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-12 22:10:22 +0800 |
| commit | 145b5db151277133a2cfdb2d32d1756ff7df241b (patch) | |
| tree | f225211dd9e76f26b56d71791ae7b1f52897c4a5 /gcc/range-op-float.cc | |
| parent | 8d3eb3ad5388d2f523e4a6f886c4b3364f77f51f (diff) | |
| download | gcc-145b5db151277133a2cfdb2d32d1756ff7df241b.zip gcc-145b5db151277133a2cfdb2d32d1756ff7df241b.tar.gz gcc-145b5db151277133a2cfdb2d32d1756ff7df241b.tar.bz2 | |
RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From
the user's perspective, it is reasonable to do some get/set operations
for the vfloat16*_t types when only ZVFHMIN is enabled.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat16m1_t): Add type to lmul1 ops.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Likewise.
Diffstat (limited to 'gcc/range-op-float.cc')
0 files changed, 0 insertions, 0 deletions