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authorRichard Sandiford <rdsandiford@googlemail.com>2014-06-11 16:59:17 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2014-06-11 16:59:17 +0000
commit8677664e02258772068ad1fe4672943c998bace8 (patch)
treeebbbc6a5c16fb2f71c030dc719d566bd7b2d0538 /gcc/postreload.c
parent7fd308cffa3775f62d69b63bc9b1cefced10d817 (diff)
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common.md: New file.
gcc/ * common.md: New file. * doc/md.texi: Update description of generic, machine-independent constraints. * config/s390/constraints.md (e): Delete. * Makefile.in (md_file): Include common.md. * config/m32c/t-m32c (md_file): Likewise. * genpreds.c (general_mem): New array. (generic_constraint_letters): Remove constraints now defined by common.md. (add_constraint): Map TARGET_MEM_CONSTRAINT to general_mem. Allow the first character to be '<' or '>' as well. * genoutput.c (general_mem): New array. (indep_constraints): Remove constraints now defined by common.md. (note_constraint): Map TARGET_MEM_CONSTRAINT to general_mem. Remove special handling of 'm'. * ira-costs.c (record_reg_classes): Remove special handling of constraints now defined by common.md. * ira.c (ira_setup_alts, ira_get_dup_out_num): Likewise. * ira-lives.c (single_reg_class): Likewise. (ira_implicitly_set_insn_hard_regs): Likewise. * lra-constraints.c (reg_class_from_constraints): Likewise. (process_alt_operands, process_address, curr_insn_transform): Likewise. * postreload.c (reload_cse_simplify_operands): Likewise. * reload.c (push_secondary_reload, scratch_reload_class) (find_reloads, alternative_allows_const_pool_ref): Likewise. * reload1.c (maybe_fix_stack_asms): Likewise. * targhooks.c (default_secondary_reload): Likewise. * stmt.c (parse_output_constraint): Likewise. * recog.c (preprocess_constraints): Likewise. (constrain_operands, peep2_find_free_register): Likewise. (asm_operand_ok): Likewise, but add a comment saying why 'o' must be handled specially. From-SVN: r211475
Diffstat (limited to 'gcc/postreload.c')
-rw-r--r--gcc/postreload.c18
1 files changed, 2 insertions, 16 deletions
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 5b18fc7..9d71649 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -553,22 +553,8 @@ reload_cse_simplify_operands (rtx insn, rtx testreg)
switch (c)
{
- case '=': case '+': case '?':
- case '#': case '&': case '!':
- case '*': case '%':
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- case '<': case '>': case 'V': case 'o':
- case 'E': case 'F': case 'G': case 'H':
- case 's': case 'i': case 'n':
- case 'I': case 'J': case 'K': case 'L':
- case 'M': case 'N': case 'O': case 'P':
- case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
- /* These don't say anything we care about. */
- break;
-
- case 'g': case 'r':
- rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
+ case 'g':
+ rclass = reg_class_subunion[rclass][GENERAL_REGS];
break;
default: